International Business Machines Corporation

Matthias Braendli

Marcel A Kossel

Pier Andrea Francese

Thomas E Morf

Mridula Prathapan

Peter Mueller

Cezar Bogdan Zota

Abdullah Serdar Yonar

Vishal Khatri

The invention is notably directed to a voltage-to-time converter comprising a first interleaving stage configured to perform a sampling of an input voltage, thereby generating a first set of sampled voltage signals. The first interleaving stage is further configured to perform a first voltage-to-time conversion in an interleaved manner, thereby generating a first set of time-interleaved signals in the time domain. A second interleaving stage is configured to perform a time-to-voltage conversion of the first set of time-interleaved signals, thereby generating a second set of sampled voltage signals. The second interleaving stage is further configured perform a second voltage-to-time conversion in an interleaved manner, thereby generating a second set of time-interleaved signals in the time domain. The invention further concerns a related design structure and a related method.

Time domain interleaving

The invention relates to a control unit for controlling a data transfer between a classical processor and a quantum processor with a plurality of qubits. The control unit comprises a plurality of control and read-out circuits configured for controlling and reading out the plurality of qubits. Each of the control and read-out circuits is assigned to one or more of the qubits. A controlling of the quantum processor by the control unit comprises selectively powering on a subset of the control and read-out circuits during an instruction cycle, while ensuring that the remaining control and read-out circuits are powered off during the instruction cycle. The powered-on subset of control and read-out circuits is used to control a subset of the qubits and to read out data from the subset of qubits.

Control unit for qubits

The present disclosure relates to a method for quadrature error correction using a frequency divider circuit. The method comprises delaying input of data to master input terminals and/or slave input terminals of the frequency divider circuit for correcting a quadrature error between the in-phase and quadrature-phase output signals.

Clock divider with quadrature error correction

The invention relates to a receiving unit for performing a calibration of a reference voltage, comprising a reference voltage unit for generating and applying a reference voltage on the evaluation unit depending on a converter value, an evaluation unit for receiving a single-ended data signal and being configured to determine an evaluation signal based on the data signal and the reference voltage, and a logic unit configured to perform a calibration process for calibrating the reference voltage. The logic unit is configured to command a memory device to apply a permanent digital logical state on a data line, to iteratively adapt a converter voltage to substantially match the voltage level of the logical state on the data line, and to determine the reference voltage depending on the converter voltage for which the voltage level of the logical state on the data line has been substantially matched.

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Otelfingen, Switzerland

Matthias Braendli