Advanced Micro Devices Corporation

Globalfoundries Inc.

Matthias Baer

Ralf Flemming

Uwe Eckhardt

Stephan Rosner

Stephen T Novak

William F Kern

Sreenivasa Chalamala

Dirk Fimmel

Karl-Heinz Sandig

Juergen Boldt

Attila Roemer

Peer Schlegel

Falk Tischer

Steffen Hofmann

Oliver Goetting

The present disclosure relates to circuit structures and, more particularly, to circuit structures which detect high speed and high precision characterization of VTsat and VTlin of FET arrays and methods of manufacture and use. The circuit includes a control loop comprised of a differential amplifier, a plurality of FET arrays, and at least one analog switch enabling selection between a calibration mode and an operation mode.

High speed and high precision characterization of VTsat and VTlin of FET arrays

An integrated circuit including a first power rail, a second power rail, a power clamp connected between the first and second power rails; and a trigger circuit connected to the power clamp and the first second power rails. The trigger circuit includes an RC element formed on the basis of field effect transistors, first inverter stage connected to the RC element, a second inverter stage, and a third inverter stage. The first, second and third inverter stages are connected in series to a control input of the power clamp. The trigger circuit also included a feed back connection from an output of the second inverter stage to the first inverter stage.

ESD power clamp with stable power start up function

A digital compensation of an input stage of a comparator may be achieved by providing switched load elements, which may be appropriately connected to the differential input pair of the comparator in order to match transistor characteristics of the input pair and also match the load value of the input stage. Thus, enhanced offset behavior may be accomplished without providing an external signal and/or without requiring complex reference voltages/currents.

Analog comparator comprising a digital offset compensation

A wireless computer system () is formed to have a host section () and a wireless hardware section (). A first portion of a transmission frame is formed in system memory () of a host section () and a second portion of the transmission frame is formed in the wireless hardware section (). The wireless hardware section () begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory () into the wireless hardware section ().

Wireless computer system with queue and scheduler

A method of performing encrypted WLAN communication is provided that comprises the steps of performing a connection set-up for the encrypted WLAN communication and performing data frame encapsulation and/or decapsulation during the encrypted WLAN communication. The connection set-up is performed by executing software-implemented instructions, and the data frame encapsulation and/or decapsulation is performed by operating single-purpose hardware. In embodiments, corresponding single-purpose hardware devices, integrated circuit chips, computer program products and computer systems are provided. The embodiments may provide an improved hardware/software architecture for 802.11i security enhancement.

Hardware/software partitioning for encrypted WLAN communications

A communication device for performing cryptographically secured communication in a WLAN (Wireless Local Area Network) network is provided that comprises a security enhancement unit and a MAC (Medium Access Control) unit. The security enhancement unit is for encrypting plaintext data frames into encrypted data frames and/or decrypting encrypted data frames into plaintext data frames. The MAC unit is for managing communication between communication devices within the WLAN network by coordinating access to a shared wireless communication medium through which communication signals are transmitted. The security enhancement unit and the MAC unit are adapted to perform an on-the-fly encryption process and/or on-the-fly decryption process thereby exchanging the encrypted data frames without buffering the encrypted data frames after encryption or prior to decryption, respectively. The embodiments may provide an improved encryption/decryption architecture including an on-chip memory for performing on-the-fly encryption and/or on-the-fly decryption in the framework of 802.11i security enhancement.

On-the-fly encryption/decryption for WLAN communications

A memory access technique is provided that may be used in WLAN (Wireless Local Area Network) communication devices. An on-chip memory has multiple memory circuits forming individually addressable memory segments. An arbitration unit arbitrates between multiple requesters, each requesting access to the on-chip memory. The requesters are on-chip circuits and/or external devices. The arbitration unit determines a memory circuit to be accessed for each request that is received from a requester. The determination may be based on a software configurable arbitration scheme. The memory segments may form a bank of single-port SRAM (Static Random Access Memory) devices.

Growing community of inventors

Hohenstein-Ernstthal, Germany

Matthias Baer