Lenovo (singapore) Pte. Ltd.

Matthew Weber

Paul Daniel Kangas

Timothy M Wiwel

Robert Diokno

A memory system for a computer is provided as well as a method for integrity testing a memory interface. The memory system includes a memory controller providing a memory interface including a plurality of data lanes, wherein each of the plurality of data lanes includes a driver and a receiver, and wherein each receiver has an output. The memory system further includes an AND gate having an output and a plurality of inputs, wherein the output of each receiver is coupled to one of the plurality of inputs of the AND gate. The method includes driving a high signal pulse onto each of a plurality of data lanes of a memory interface, receiving a reflection of the high signal pulse on each of the data lanes, and determining whether the reflections received on the data lanes indicate that any one or more of the data lanes is defective.

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Wake Forest, NC, United States of America

Matthew Weber