Pmc-sierra, Inc.

Pmc-sierra Us, Inc.

Matthew W McAdam

Anthony Eugene Zortea

Jurgen Hissen

John Philip Plasterer

William Michael Lye

Francis Beaudoin

Andrew S Wright

Graeme Barclay Boyd

Mark Hiebert

Bill M Lye

Trent Owen McKeen

Methods and apparatus for reducing sensitivity to nonlinearities in the receiver of a digital communications system are disclosed. One aspect can be referred to as a Post-Distortion Decision Feedback Equalizer (PDFE). A gain stage is often implemented as a variable gain amplifier (VGA), and can introduce significant nonlinearities, a problem exacerbated by signals with a large peak-to-average ratio (PAR). One embodiment provides feed forward information from the VGA regarding its status to a DFE, and the DFE adjusts its filtering based on the provided information. The advantages are also applicable to fixed-gain amplifiers and to transversal filters.

Post-distortion filter for reducing sensitivity to receiver nonlinearities

Apparatus and methods determine a frequency associated with a relatively strong interfering signal (interferer) using relatively simple run-length counting techniques. Counts of run-lengths can be analyzed to estimate a frequency of the interferer. For example, a peak run-length can be associated with a frequency. In one embodiment, counts of run-lengths are used to construct a theoretical peak run-length, which is then associated with a frequency for the interferer. A theoretical count associated with the theoretical peak run-length can also be used as an indication of a signal strength of the interferer.

Run-length based spectral analysis

The signal strength of an out-of-channel interferer is estimated by measuring the transition density of the sign of the down-converted signal. RF interferers at a higher or lower frequency than the desired RF signal appear as high frequency content in the down-converted signal, thus increasing the likelihood of zero-crossings.

Out-of-channel received signal strength indication (RSSI) for RF front end

In a Frequency Duplex Division (FDD) radio, the transmit and receive signals are separated by frequency. In a wireless application, the power of the transmitted signal is typically much larger than the power of the received signal. A duplexer is used to separate the transmit and receive signals. Despite the operation of the duplexer, a residual transmit signal, or echo, can be present at the receiver input as a result of finite attenuation in the duplexer and other sources of transmit to receive crosstalk. With a relatively linear low-noise amplifier (LNA) and output limited mixer linearity, the echo can be cancelled in analog baseband directly at the mixer output using an out-of-channel signal indicator as the error signal for an echo control loop.

Echo cancellation for duplex radios

A method and apparatus are provided for reducing, and preferably substantially eliminating, data-pattern autocorrelations found in digital communication systems. The method employed is referred to as Data Subset Selection (DSS) and is implemented in the form of DSS engine. Autocorrelations in the data-pattern can cause many digital adaptive systems to converge to an incorrect solution. For example, the LMS method, which is often used in adaptive filtering applications, can converge to an incorrect set of filter coefficients in the presence of data-pattern autocorrelations. Digital timing recovery methods are also susceptible. Other impairments that result from data-pattern autocorrelations include increased convergence time and increased steady-state chatter. DSS reduces, and preferably substantially eliminates, data-pattern autocorrelations by selecting a subset of the data stream that either demonstrates smaller autocorrelations or no autocorrelations, thus improving the performance of the aforementioned digital adaptive systems.

Data subset selection algorithm for reducing data-pattern autocorrelations

A biasing circuit and method for minimizing distortion in a MOS transistor. A first CW source provides a first CW signal at the input of a replica transistor to obtain an output signal at the output of the replica transistor. The output signal is mixed with another CW signal having a frequency equal to N times that of the first CW signal, N being an integer greater than one, to obtain a mixed signal having a DC component with an intensity proportional to the N-order distortion present in the output signal. A bias voltage to minimize this distortion is then applied to the input of the original transistor on which the replica transistor is based, the bias voltage determined in accordance with the intensity of the DC component.

Continuous wave based bias method and apparatus for minimizing MOS transistor distortion

Methods and apparatus control the gain of an RF amplifier. In an example, the RF amplifier is biased for low distortion. The bias is not changed to adjust gain. Rather, the amplifier's gain is controlled by selectively activating or deactivating RF amplifier cells of the RF amplifier. This individual RF amplifier cells to be biased for good linearity and relatively good spectral performance, while permitting gain control.

Techniques to control amplifier gain over process, voltage, and/or temperature (PVT) variations

A method and apparatus for linearizing the gain of a common-source field effect transistor (FET) amplifier. The method involves connecting a capacitive load in parallel with the gate of the FET through a switch, and opening and closing this switch depending on the voltage on the gate of the FET. The result is a FET amplifier circuit that has a substantially linear transcapacitance characteristic, making it a useful circuit for low-distortion high-power amplifiers such as xDSL line drivers.

Method for enhancing linearity of a transistor amplifier using switched capacitive loads

An apparatus and method are provided for equalizing a dispersive channel based on in-phase and quadrature samples corresponding to an input signal. An equalizer according to the present invention uses a novel adaptation algorithm to adjust filtering characteristics based on previous in-phase samples and a current quadrature sample. The adaptation algorithm is configured to update filter coefficients in response to detecting a transition in the in-phase samples. The equalizer provides equalization for quadrature post-cursor intersymbol interference (ISI) components of the input signal. In an embodiment, the equalizer also provides equalization for in-phase post-cursor ISI components, quadrature precursor ISI components, in-phase precursor ISI components, or a combination of the forgoing.

In-phase and quadrature decision feedback equalizer

A flexible adaptation engine includes a coefficient adaptation circuit that implements multiple adaptation algorithms, and/or multiple coefficient selection algorithms, to adapt the filter coefficients of one or more digital filters, such as the transversal filters of a receiver. In one embodiment, a controller selects the filter coefficients to be adapted, and the adaptation algorithm(s) to be used to adapt the selected coefficients, based on various criteria such as convergence status data, clock recovery status signals, the current load on a processor that adapts the coefficients, and/or manual control signals. In one embodiment, the architecture supports the ability to vary the number of coefficients that are updated at a time, and to concurrently apply different adaptation algorithms to different subsets of filter coefficients. The flexible adaptation engine may be implemented in application-specific hardware and/or as a processor that executes software.

Flexible adaptation engine for adaptive transversal filters

A method and apparatus for creating high speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads and the biasing of these logic cells is disclosed. The logic cells can include, for example, buffers, AND gates, OR gates, flip-flops, and latches. The current steering cells with actively-peaked loads can provide benefits such as reduced power consumption, smaller area, and higher speed performance over conventional devices. This performance boost is preferably achieved using NMOS followers with resistively degenerated gates to create frequency peaked transfer function of current-mode logic cells. These logic cells with actively-peaked loads can advantageously be used in circuits in which relatively good power area and performance are desired for state machine logic, parallel to serial conversions, serial to parallel conversions, and the like.

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Vancouver, Canada

Matthew W McAdam