Intel Corporation

Matthew W Heath

Robert J Greiner

Mark R Waggoner

Brett W Newkirk

Igor V Molchanov

David Dehnert

In one embodiment, a timing relationship between two signals on an integrated circuit is measured using a ring oscillator on the die of the integrated circuit. The measured time difference is outputted in a digital form. A delay line coupled to the ring oscillator may be used to reduce uncertainty in measurement which may result from the effects of latch circuit metastability. Other embodiments are described and claimed.

On-die signal timing measurement

A test architecture and method of testing are disclosed to allow multiple scan controllers, which control different scan chain designs in multiple logic blocks, to share a test access mechanism. During test mode, the test architecture is configured to decouple clock sources of the test access mechanism, the scan controllers and the scan chains.

Decoupled clocking in testing architecture and method of testing

A detector to detect the magnitude of the jitter that may occur in a first clock signal and a second clock signal and to generate an alarm signal if the magnitude of the jitter exceeds the threshold value. The detector comprises a one-hot register storing a one-hot value comprising a first logic bit (=1) centered around one or more second logic bits (=0). The detector comprises a threshold register storing a threshold value comprising one or more second logic bits centered around one or more first logic bits. An event of a first clock rotates the contents of the one-hot value and an event of a second clock rotates the contents of the threshold value. A match between the pre-specified bit of the one-hot value and the threshold value indicates the occurrence of the jitter having a magnitude greater than the threshold value.

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Hillsboro, OR, United States of America

Matthew W Heath