Agere Systems Inc.

Lsi Corporation

Matthew Tota

Martin S Dell

Mohammad Shafiul Mobin

Wei Li

Yung-Terng Wang

Robert H Leonowich

Zbigniew M Dziong

Gregory Scott Winn

Mehran Aliahmad

Joseph A Manzella

Mark Trafford

Ayal Shoval

Jack Lee

Yu-Kuen Ouyang

John Leshchuk

Walter A Roper

A signal generator circuit for reducing power consumption of out-of-band message communications between a first device including the signal generator circuit and a second device coupled to the first device comprises a switching circuit and a controller coupled to the switching circuit. The controller is operative to receive a reference clock signal and at least a first control signal indicative of a request for the first device to send a message to the second device when the first device is in a first mode of operation. The controller generates an output control signal and an output data signal. The output control signal is operative as a function of the first control signal to selectively power up the switching circuit and a transmitter driver during the first mode. The output data signal includes the message supplied to the transmitter driver for transmission to the second device during the first mode.

Methods and apparatus for low power out-of-band communications

Methods and apparatus are provided for automatic gain control in a receiver using samples taken at a desired sampling phase and target voltage level. The gain of a received signal is adjusted by obtaining a plurality of samples of the received signal substantially at a desired sampling phase (such as a center of a given unit interval), wherein at least one of the samples is taken substantially at a target voltage level; comparing the plurality of samples to determine whether the received signal has an amplitude that is substantially equal to the target voltage level; and adjusting a receiver gain based on whether the received signal amplitude is substantially equal to the target voltage level. The comparison can comprise the evaluation of a logic function, such as an exclusive OR function. The comparison can be performed over a plurality of samples to obtain an average gain update decision. The receiver gain can be adjusted based on a histogram of the average gain update decision, relative to a predefined threshold.

Methods and apparatus for automatic gain control using samples taken at desired sampling phase and target voltage level

In described embodiments, a transceiver supports two or more rates using an oversampling clock and data recovery (CDR) circuit sampling high rate data with a predetermined CDR sampling clock. A timing recovery circuit detects and accounts for extra or missing samples when oversampling lower rate data. An edge detector detects each actual data symbol edge and provides for an edge decision offset in a current instant's block of samples. An edge error is generated from the previous instant's actual and calculated edges; and an edge distance between actual edges of the current and previous instants is generated. Filtered edge distance and error are combined to generate a calculated edge position for the data symbol edge for the current instant. The edge decision offset is applied to the current calculated edge position to identify a sample value to generate a decision for the data symbol to detect the current data value.

Oversampled clock and data recovery with extended rate acquisition

A switch fabric for routing data has a switching stage configured between an input stage and an output stage. The input stage forwards the received data to the switching stage, which routes the data to the output stage, which transmits the data towards destinations. In one aspect, at least one input port can be programmably configured to store data in two or more input routing queues that are associated with a single output port, and at least one output port can be programmably configured to receive data from two or more output routing queues that are associated with a single input port. In another aspect, the output stage transmits status information about the output stage to the input stage, which uses the status information to generate bids to request connections through the switching stage. In yet another aspect, the switching stage transmits a grant/rejection signal to the input stage identifying (1) whether each bid is accepted or rejected and, if rejected, (2) a reason for rejecting the bid, and the input stage determines how to react to a rejected bid based on the reason the bid was rejected.

Three-stage switch fabric with input device features

In one embodiment, queues associated with a first traffic class (FTC) are selected for service. Each FTC queue having at least one enqueued cell is identified as an occupied FTC queue, Where at least one FTC queue is provisioned for burst scheduling of multiple cells when serviced. An occupied FTC queue provisioned for burst scheduling is identified as a super-occupied FTC queue when the number of cells enqueued is greater than a specified number. Each occupied FTC queue is set as eligible for service based on a FTC scheduling algorithm. An eligible FTC queue is selected for service based on a corresponding sub-priority of each eligible FTC queue. Each FTC queue is assigned a sub-priority based on a service level of a connection associated with enqueued cells. When the super-occupied queue is serviced, the number of cells dequeued is based on a burst size.

Scheduler for a packet routing and switching system

A switch fabric for routing data has a switching stage configured between an input stage and an output stage. The input stage forwards the received data to the switching stage, which routes the data to the output stage, which transmits the data towards destinations. Each input device of the input stage transmits bids to the crossbar devices of the switching stage to request connections through the switching stage for routing the data to the output devices of the output stage. In one aspect, each crossbar device has (1) a bid arbitrator that determines whether to accept or reject each received bid, wherein, in response to a collision between multiple bids, the bid arbitrator accepts two or more of the colliding bids in a single time slot; and (2) memory for storing one or more accepted cells for the same output device, wherein the crossbar device can transmit grant signals for two or more accepted bids for the same output device in a single time slot. In another aspect, the bid arbitrator is configured to re-consider whether to accept a stored bid that was not accepted in a previous time slot.

Three-stage switch fabric with buffered crossbar devices

A multiple data-rate receiver uses a signal rate detection technique that employs comparators to obtain information on the incoming data rate for enabling the appropriate receiver. Once a data rate is determined, only then is the appropriate receiver activated. Hence, power dissipation is kept to a minimum during the autonegotiation phase. This is a significant improvement over existing art which require two (or more) receivers to be active during the autonegotiation phase, consequently demanding high power dissipation. Because the autonegotiation phase can be lengthy, the present technique is preferable in many cases.

Low power signal detection for autonegotiation

An auto-detection system and method for a network transceiver that allows the network transceiver to switch from a first rate mode to a second rate mode automatically. In one embodiment, the system includes: (1) an error counter, coupled to a receive input of the network transceiver, that accumulates a count of code violations while the network transceiver is operating in the first rate mode and (2) mode-switching circuitry, coupled to the error counter, that switches the network transceiver to the second rate mode when the count reaches a predetermined value.

Auto-detection system and method for a network transceiver

Integrated circuits are disclosed which implement multiple channel media access control devices for controlling network communications. The integrated circuits include multiple channel slices which output data for transmission through the network. Each of the channel data are input to a single data memory, which reduces the size of the integrated circuit. Since only one data memory is used to buffer data from multiple channels, the data are first retimed from individual media access control circuit clock domains to a common host clock domain and then scheduled for output to the host. By retiming the data, integrated circuit signal throughput is enhanced. Deeply embedded transmit and receive FIFOs are provided to receive the channel data and implement shared memory access.

System with a plurality of media access control circuits with a shared memory for storing data and synchronizing data from a clock domain to a host clock domain

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Clinton, NJ, United States of America

Matthew Tota