Cisco Technology, Inc.

Matthew Todd Lawson

Mick R Jacobs

Neil Sharma

David Walker

Kenneth Michael Rose

Mohammad Issa

Aviran Kadosh

Michael A Benning

Stephen Patrick Kolecki

Vijay A Nebhrajani

Jason Allen Marinshaw

Rajashekar Reddy Bussa

Lewis Leo Butler, Ii

Sai Kishore Vavilala

Jason A Marinshaw

Devices, systems, methods, and processes for transmitting and receiving one or more data packets are described herein. A device may face an internal non-deterministic delay in processing causing a gap or an interruption during transmission of the data packet. During the gap, the device can transmit one or more Intra-Packet Idle (IPI) words between the transmission of the data packet. The IPI words can be ignored or discarded by a receiver. The device may transmit the data packet into multiple parts by transmitting the IPI words between the parts. The receiver can receive the parts of the data packet and the IPI words and retrieve the data packet based on the parts of the data packet. The device may set a configurable threshold value indicative of a maximum number of the IPI words that can be transmitted during the gap of the interruption, such that the receiver can efficiently identify and discard a runt packet. The device does not require a buffer to fetch and store the data packet prior to the transmission, thereby eliminating a latency caused by the buffer.

Systems and methods of inserting idles within packets to reduce latency

Techniques for forward error correction are disclosed. These techniques include receiving a forward error correction codeword transmitted over a communication network, the codeword including a parity portion and a payload portion. The techniques further include determining, based on the parity portion, to disable forward error correction for the codeword. The techniques further include disabling forward error correction for the codeword.

Forward error correction bypass for reduced power

In one embodiment, a method includes receiving an input signal at a local data lane comprising a dynamic entry shift register, the input signal comprising a marker also received at a remote data lane, identifying receipt of the marker in the local data lane, starting a timer and notifying the remote data lane that the marker was found, receiving a marker found status from the remote data lane and saving a value of the timer, calculating a compensated delay for the remote data lane based on the timer value and a number of pipeline stages for the remote data lane, and setting an entry point to the dynamic entry shift register based on the compensated delay to deskew data between the local data lane and the remote data lane.

Method and apparatus for deskewing decentralized data streams

A method for performing packet reorder processing is disclosed. The method comprises receiving, at a packet receive buffer, a data packet, the packet receive buffer comprising a plurality of N-sized pages. The method also comprises storing the received data packet across a plurality of pages of the packet receive buffer. The method further comprises writing, at storage of each of the plurality of pages, a pointer to a next page in which a subsequent portion of the data packet is stored. The method also comprises transmitting the pointer to a ring buffer. The method further comprises calculating an offset to the ring based on a sequence number of the corresponding packet, and storing the pointer to a first page in the calculate offset of the ring buffer.

Systems and methods for performing packet reorder processing

A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header may include an invert bit to alter the majority sign of an n-bit portion. Other aspects of the present invention are also described herein.

Fabric channel control apparatus and method

A channel synchronization method in which local serializers serially transmits first n-bit codes, respectively, to remote deserializers, respectively. Also local deserializers serially receive first n-bit codes, respectively, from remote serializers, respectively. One of the first n-bit codes transmitted to one of the remote serializers indicates one of the local deserializers is not link aligned.

Mechanism for channel synchronization

A self-adjusting load balancing among multiple fabric ports. A plurality of first values is received in response to receiving a first frame, wherein each of the first values is related to a quantity of data stored in a respective one of a plurality of buffers of fabric ports. First identifiers are also received, each of which corresponds to a respective one of a first subset of the plurality of buffers. A subset of the first identifiers is selected based on one or more of the first values. Thereafter one of the first identifiers contained in the selected subset is selected. Ultimately the first frame is transmitted to the buffer that corresponds to the selected one of the first identifiers.

Self-adjusting load balancing among multiple fabric ports

Computer-readable media, apparatus and other embodiments associated with performing comma alignment with scrambled data are described. One example method includes controlling an apparatus to generate a data stream that facilitates achieving and determining alignment in a device. The data stream includes sequences of N random portions of Y-bit characters followed by a Z-bit alignment character, N, Y and Z being integers. Another example method includes controlling an apparatus to receive and examine the data stream. The method also includes generating an alignment signal upon determining an alignment for recovered data in the device.

Comma alignment with scrambled data

A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header includes a CRC to provide improved error detection.

Enhanced error detection in multilink serdes channels

Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with a shift register with a dynamic entry point, which may particularly useful for aligning skewed data. The dynamic entry shift register typically includes a series of storage elements, with multiplexers distributed between the storage elements. Each of the multiplexers is configured to select between: (a) the output signal of a previous storage element, and (b) the input signal. A control is configured to configure the multiplexers for a data signal applied as the input signal to induce an appropriate delay of the data signal as the output signal. The dynamic entry shift register can be scaled to accommodate a longer delay while still using only 2:1 multiplexers between stages in the dynamic entry shift register(s).

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Grass Valley, CA, United States of America

Matthew Todd Lawson