Motorola Corporation

Freescale Semiconductor,inc.

Globalfoundries Inc.

Matthew Thomas Herrick

Cindy Reidsema Simpson

Terry Grant Sparks

Nigel Graeme Cave

James Derek Legg

Gregory S Etherington

Gowrishankar L Chindalore

Robert F Steimle

Joy Kimi Watanabe

Ramachandran Muralidhar

Olubunmi O Adetutu

Sung-Taeg Kang

Sunil Kumar Singh

Ko-Min Chang

Rajesh A Rao

Tab Allen Stephens

Paul Grudowski

Robert W Fiordalice

Mohammed Rabiul Islam

Dean J Denning

Norman Chen

Teck Jung Tang

Ajay Jain

Dewei Xu

Ramnath Venkatraman

Yuyang Sun

Sohan Singh Mehta

Narayanan C Ramani

Cristiano Capasso

Shyam Pal

Jeong Soo Kim

Gregor Braeckelmann

Rina Chowdhury

Marijean E Azrak

Robert Douglas Mikkola

Edward Acosta

David Moralez Pena

Brett Caroline Baker

Cindy Kay Goldberg

Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.

Method for fabricating a semiconductor integrated circuit with a litho-etch, litho-etch process for etching trenches

Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure.

Reduced capacitance interlayer structures and fabrication methods

A method includes forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer; forming an opening; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gate material over the charge storage layer; removing a portion of the second layer and a portion of the charge storage layer which overlie the hard mask layer, wherein a second portion of the second layer remains within the opening; forming a patterned masking layer over the hard mask layer and over the second portion, wherein the patterned masking layer defines both a first and second bitcell; and forming the first and second bitcell using the patterned masking layer, wherein each of the first and second bitcell comprises a select gate made from the first layer and a control gate made from the second layer.

Method of making a split gate memory cell

A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently formed overlying and adjacent to the select gate. A control gate is subsequently formed adjacent to and separated from the select gate by the charge storing layer. The charge storing layer is also positioned between the control gate and the semiconductor substrate. The control gate initially has a height greater than the predetermined height of the select gate. The control gate is recessed to a control gate height that is less than the predetermined height of the select gate. A source and a drain are formed in the semiconductor substrate.

Method of forming a split gate non-volatile memory cell

A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.

Method of forming a via

A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.

Method for forming a split gate memory device

An electroplating system () and process makes electrical current density across a semiconductor device substrate () surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (and) reduce the electrical current density near the edge of the substrate (). By reducing the current density near the edge of the substrate (), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (). The system can also be modified so that the material that plates on electrical current density modifier portions () of structures () can be removed without having to disassemble any portion of the head () or otherwise remove the structures () from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

Process for depositing a layer of material on a substrate

In one embodiment, a first dielectric film ( ), and a second dielectric film ( ) are formed over a substrate ( ). The substrate is cured to at least partially change a property of the second dielectric film thereby forming an intermediate etch stop ( ). A third dielectric film ( ) is formed over the substrate ( ). The substrate ( ) is then etched to remove portions of the first dielectric film ( ) and portions of the third dielectric film ( ) using the intermediate etch stop ( ) to form a portion of an interconnect opening ( ). In an alternative embodiment, a resist layer ( ), and portions of an interlevel dielectric layer ( ) are etched. Upon completion of the step of etching, the photoresist layer ( ) and portions of the interlevel dielectric layer ( ) are completely removed.

Method for forming an opening in a semiconductor device substrate

An electroplating system ( ) and process makes electrical current density across, a semiconductor device substrate ( ) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers ( and ) reduce the electrical current density near the edge of the substrate ( ). By reducing the current density near the edge of the substrate ( ), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate ( ). The system can also be modified so that the material that electrical current density modifier portions ( ) on structures ( ) can be removed without having to disassemble any portion of the head ( ) or otherwise remove the structures ( ) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

In accordance with embodiments of the present invention a trench-level dielectric film ( ) and a via-level dielectric film ( ) are formed overlying a semiconductor device substrate ( ). A via opening ( ) is etched in the trench-level dielectric film with a first etch chemistry that has a higher etch selectivity to the trench-level dielectric film ( ) than to the via-level dielectric film ( ). A trench opening ( ) is patterned in a photoresist layer ( ) overlying the trench-level dielectric film ( ). The via-level dielectric film ( ) is etched with a second etch chemistry to extend the via opening ( ) into the via-level dielectric film ( ). The trench-level dielectric film ( ) is etched to form a trench opening.

Method for forming a semiconductor device

A method for electroplating a copper layer (,) over a wafer (,) powers a cathode of an electroplating system (,) in a manner that obtains improved copper interconnects. A control system (,) powers the cathode of the system (,) with a mix of two or more of: (i) positive low-powered DC cycles (,or,); (ii) positive high-powered DC cycles (,or,); (iii) low-powered, pulsed, positive-power cycles (,or,); (iv) high-powered, pulsed, positive-powered cycles (,or,); and/or (v) negative pulsed cycles (,or,). The collection of these cycles functions to electroplate copper or a like metal (,) onto the wafer (,). During electroplating, insitu process control and/or endpointing (,or,) is performed to further improve the resulting copper interconnect.

Method for forming a copper layer over a semiconductor wafer

In one embodiment, a first dielectric film (,), and a second dielectric film (,) are formed over a substrate (,). The substrate is cured to at least partially change a property of the second dielectric film thereby forming an intermediate etch stop (,). A third dielectric film (,) is formed over the substrate (,). The substrate (,) is then etched to remove portions of the first dielectric film (,) and portions of the third dielectric film (,) using the intermediate etch stop (,) to form a portion of an interconnect opening (,). In an alternative embodiment, a resist layer (,), and portions of an interlevel dielectric layer (,) are etched. Upon completion of the step of etching, the photoresist layer (,) and portions of the interlevel dielectric layer (,) are completely removed.

Method of forming a semiconductor device

An interconnect (,) is formed overlying a substrate (,). In one embodiment, an adhesion/barrier layer (,), a copper-alloy seed layer (,), and a copper film (,) are deposited overlying the substrate (,), and the substrate (,) is annealed. In an alternate embodiment, a copper film is deposited over the substrate, and the copper film is annealed. In yet another embodiment, an adhesion/barrier layer (,), a seed layer (,), a conductive film (,), and a copper-alloy capping film (,) are deposited over the substrate (,) to form an interconnect (,). The deposition and annealing steps can be performed on a common processing platform.

An electroplating system (,) and process makes electrical current density across a semiconductor device substrate (,) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (,and,) reduce the electrical current density near the edge of the substrate (,). By reducing the current density near the edge of the substrate (,), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (,). The system can also be modified so that the material that electrical current density modifier portions (,) on structures (,) can be removed without having to disassemble any portion of the head (,) or otherwise remove the structures (,) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

Process for depositing a layer of material over a substrate

In accordance with embodiments of the present invention a trench-level dielectric film (26) and a via-level dielectric film (24) are formed overlying a semiconductor device substrate (10). A via opening (42) is etched in the trench-level dielectric film with a first etch chemistry that has a higher etch selectivity to the trench-level dielectric film (26) than to the via-level dielectric film (24). A trench opening (54) is patterned in a photoresist layer (52) overlying the trench-level dielectric film (26). The via-level dielectric film (24) is etched with a second etch chemistry to extend the via opening (42) into the via-level dielectric film (24). The trench-level dielectric film (26) is etched to form a trench opening.

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Austin, TX, United States of America

Matthew Thomas Herrick