International Business Machines Corporation

Globalfoundries Inc.

Matthew Thomas Guzowski

Michael S Gray

Kevin W McCullen

Jason D Hibbeler

Robert F Walker

Xin Yuan

David S Wolpert

David Brian Stone

Leon Jacob Sigal

Timothy W Budell

Stephen Larry Runyon

Xiaoping Tang

Rani Narayan

Craig P Lussier

Veit Gernhoefer

Robert Charles Cusimano

Richard Dauphin

Adam Matthew Bittner

Patrick G Wilder

Xiaoyun K Wu

Dureseti Chidambarrao

Lars W Liebmann

Gustavo Enrique Tellez

Michael H Wood

Robert J Allen

Steven Paul Ostrander

Daniel Nelson Maynard

Christopher J Gonzalez

Tuhin Sinha

Atsushi Ogino

Alexander Ivrii

Evanthia Papadopoulou

Erwin Behnen

Mervyn Y Tan

Sarah C Braasch

Pieter J Woeltgens

Stephen I Runyon

Bruce C Wheeler

Michael Gester

Method and apparatus for generating an updated power delivery network. Generating the power delivery network includes determining power characteristics for a power delivery network of a circuit design based on logic cells of the circuit design. The power delivery network includes power wires and power staples connecting pairs of the power wires to each other. Further a first one or more of the power staples is remove from the power delivery network based on the power characteristics. Signal wires for the logic cells are routed after removing the first one or more of the power staples. Routing the signal wires includes routing a first signal wire of the signal wires in a routing track corresponding to the first one or more of the power staples.

Generating a power delivery network based on the routing of signal wires within a circuit design

A structure including a plurality of dielectric regions is described. The structure can include a rivet cell. The rivet cell can include a set of stacked vias. The rivet cell can extend through a stress hotspot of the structure. A length of the rivet cell can thread through at least one dielectric region among the plurality of dielectric regions. The rivet cell can be among a number of rivet cells inserted in the stress hotspot. The stress hotspot can be among a plurality of stress hotspots across the structure. A length of the rivet cell can be based on a model of a relationship between the length of the rivet cell and an energy release rate of the structure. The rivet cell can thread through an interface between a first dielectric region and a second dielectric region having different dielectric constants.

Stacked via rivets in chip hotspots

Aspects include techniques for selective boundary overlay insertion for hierarchical circuit design. A method may include determining, by a processing device, a block type of a child block. The method may further include electively inserting, by the processing device, at least one of an instantiated boundary overlay and a merged boundary overlay into the hierarchical circuit design based on the block type of the child block. The instantiated boundary overlay enables a parent block to pass a testing at an out-of-context level, and the merged boundary overlay enables the parent block to continue to pass the testing when the child block is inserted into the parent block associated with the child block.

Selective boundary overlay insertion for hierarchical circuit design

Methods of the present disclosure can include: using a computing device to perform actions including: applying a design rule check (DRC) on a proposed integrated circuit (IC) layout, wherein the DRC applies a set of restrictive design rules (RDRs) in response to the proposed IC layout being a contact area (CA) layout; computing a conflict graph for the proposed IC layout in response to one of the IC layout being a metal layer layout and the set of RDRs being satisfied; determining whether the IC layout is one of non-colorable, indeterminate, partially colorable, and fully colorable; and partially coloring the IC layout and identifying non-colorable nodes in response to the IC layout being indeterminate or partially colorable.

Reducing color conflicts in triple patterning lithography

Approaches are provided for fixing pin mismatches from swapping library cells in layout migration. Specifically, a method is provided that includes collecting information about a first technology pin from a library cell in a first technology. The method further includes swapping the library cell in the first technology with a library cell in a second technology. The method further includes collecting information about a second technology pin from the library cell in the second technology. The method further includes building a pin-mapping table that is configured to map the first technology pin to the second technology pin. The method further includes scaling a layout from the first technology to the second technology. The method further includes modifying the layout based on the pin-mapping table to match the at least one first technology pin to the at least one second technology pin while satisfying ground rules of the second technology.

Systems and methods for fixing pin mismatch in layout migration

An adaptive weighting method for layout optimization differentiates different priorities by assigning the weight of a higher priority (p) to be multiple of the weight of a lower priority (p) where W(p)=m% W(p. To avoid numerical imprecision, this method keeps the total cost in the objective function within a trustable range by scaling the initial weights in the objectives, while maintaining relativity, to produce the scaled weights.

Adaptive weighting method for layout optimization with multiple priorities

A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters.

Layout optimization using parameterized cells

A system and method for generating simulated wiring connections between a semiconductor device and a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to the semiconductor device and identifying a plurality of second factors and instances of each second factor relating to the carrier. The first and second factors are associated with each other on a one-to-one basis. A simulated wiring connection is generated between a first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal. A simulated wiring connection is generated between third I/O terminals located in a first region and fourth I/O terminals located in a second region.

Auto connection assignment system and method

A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.

Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design

A method, system and program product for context aware sub-circuit layout modification are disclosed. The method may include defining at least one context for the sub-circuit for each circuit that uses the sub-circuit; in the case that a plurality of contexts are defined, minimizing a number of contexts for the sub-circuit by combining contexts into at least one stage; placing each stage into a staged layout; and modifying the sub-circuit by modifying the staged layout.

Context aware sub-circuit layout modification

Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell independently with respect to the macro based on the interface strategy; initially scaling the macro; swapping the migrated base cell into the macro; and legalizing content of the initially scaled macro.

Independent migration of hierarchical designs with methods of finding and fixing opens during migration

A method of modifying a VLSI layout for performance optimization includes defining a revised set of ground rules for a plurality of original device shapes to be modified and flattening the plurality of original device shapes to a prime cell. A layout optimization operation is performed on the flattened device shapes, based on the revised set of ground rules, so as to create a plurality of revised device shapes. An overlay cell is then created from a difference between the revised device shapes and the original device shapes.

Method for implementing overlay-based modification of VLSI design layout

A system and method for generating simulated wiring connections between first I/O terminals of a semiconductor device and second I/O terminals of a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to a semiconductor device and identifying a plurality of second factors and instances of each second factor relating to a carrier. The first and second factors are associated with each other on a one-to-one basis. The instances of each first factor are correlated to the instances of each associated second factor on a one-to-one basis. A simulated wiring connection automatically is generated between each first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal.

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Essex Junction, VT, United States of America

Matthew Thomas Guzowski