Emc Corporation

Matthew Sullivan

Almir D Davis

David Iwatsuki

Robert DeCrescenzo

Paul C Wilson

Scott Romano

Oren Mano

Waiyaki O Buliro

Steven Kosto

A system for transferring data packets between a data packet transfer core and a number of clients of an application layer, including an interface between the data packet transfer core and the application layer for transferring data packets from the packet transfer core to a first client and a second client. The data packet transfer core includes a number of core buffers for receiving data packet transfers input to the data packet transfer core. Each of the number of core buffers include a cut-through data path including a register and a bypass data path, the bypass data path transferring data packets from an input to the register to an output of the register without passing through the register. The system further includes a first data path from the first interface to the first client and a second data path from the interface to the second client, the second data path including an application layer buffer having an input coupled to the interface and an output coupled to the second client, the application layer buffer being for storing data packets transmitted to the second client when data packets are transmitted to the second client at a rate that is faster than the second client is able to receive the data packets. In a first mode of operation, data packets transmitted from the data packet transfer core to the first client are transferred through the bypass data path of at least one of the number of core buffers, over the interface and directly to the first client over the first data path.

Method and system for improving the latency in a data transmission system

A system for controlling packet transfers includes a packet transfer core; an application layer coupled to the packet transfer core by an application interface; a buffer in the packet transfer core for receiving packets from a packet source and transferring the packets to the application layer over the application interface, the packets comprising one or more words; a register in the application layer for receiving packets from the application interface; and a client device for receiving packets transferred thereto from the register. When the client is unable to receive packets from the register, the client asserts a first wait signal to the register, causing the register to continue receiving packets from the interface and storing the packets without transferring the packets to the client. When the register is unable to continue receiving packets from the interface, the register asserts a second wait signal to the buffer over the application interface, causing the buffer to continue receiving packets from the packet source and storing the packets without transferring packets to the interface.

Method and system for throttling data packets in a data transmission system

A system for transferring packets between a packet transfer core and an application layer device over an application layer interface includes a buffer system disposed in the packet transfer core having an input for receiving packets from a packet source; an output for transferring packets to the application layer interface; a buffer device having an input coupled to the input of the buffer system and an output; a selection device having a first input coupled to the output of the buffer device, a control input and an output coupled to the output of the buffer system; and a bypass path coupled between the input of the buffer system and a second input of the selection device. The control input of the selection device receives a first wait signal from the application layer device which is not asserted in a first mode of operation and asserted in a second mode of operation. In the first mode of operation, packets are transferred from the input of the buffer system to the output of the buffer system via the bypass path and, in the second mode of operation, packets are transferred from the input of the buffer system to the buffer device, and are store in the buffer device without being transferred to the output of the buffer system until the first wait signal from the application layer device is deasserted.

A data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The interface includes: a global memory; a plurality of front-end directors coupled between the global memory and the host computer/server; and, a plurality of back-end directors coupled between the global memory and the bank of disk drives. Each one of the first directors and each one of the second directors has a data pipe. Each one of such front-end directors passes front-end data between the global memory and the host computer through the data pipe therein and each one of the second directors passing back-end data between the global memory and the bank of disk drives through the data pipe therein. Each one of the first and second directors includes a data pipe controller, responsive to data fed to the data pipe, for performing a selected one of a plurality of functions on the data passing through the data pipe to obtain data from the global memory or to read such data into the global memory. The function is determined by descriptors associated with the data fed to the data pipe therein. A plurality of different, independently operable state machines is provided. Each one of the state machines is adapted to produce control signals for a corresponding one to the functions. A switching section is coupled to the global memory for passing data therethrough between the global memory and the data pipe in accordance with the control signals produced by the state machines.

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Holden, MA, United States of America

Matthew Sullivan