Toshiba Memory Corporation

Ocz Storage Solutions Inc.

Matthew Stephens

Neil Buxton

Julien Margetts

A memory controller implemented within a non-volatile data storage device with improved efficiency for executing data invalidation commands is disclosed. In one embodiment, the non-volatile data storage device in communication with a host device and comprises a processor, a memory device that includes a plurality of physical storage locations, a cache memory configured to store a map table and a count value. The controller is configured to receive a data invalidation request from the host device where the request includes an execution parameter. Based on the execution parameter, the controller executes the invalidation request in an efficient and flexible manner.

Data invalidation acceleration through approximation of valid data counts

A memory controller and methods thereof suitable for operating a system utilizing multiple memory bus channels and/or multiple banks of memory devices on each channel wherein the memory devices is polled only when necessary. The memory controller includes means for determining a status of each individual memory device of the plurality of memory devices, a channel controller for each memory bus channel, and at least one status register on which is stored a plurality of bits. The channel controller maintains a derived status of each individual memory device based on the current and previous status data. Each individual bit of the plurality of bits of the status register corresponds to an individual memory device of the plurality of memory devices and indicates the derived status of the individual memory device which are used to determine whether to check for a queued command destined for the individual memory device.

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Cumbria, United Kingdom

Matthew Stephens