International Business Machines Corporation

Matthew Sean Grady

John Maxwell Cohn

Thomas Gregory Sopchak

Greg Bazan

James William Adkisson

David P Vallett

Bradley D Pepper

Leah M P Pastel

Phillip J Nigh

Louis Bernard Bushard

Frank William Angelotti

Scott A Strissel

Thomas S Barnett

David B Lutton, Ii

Robert Edward Shearer

Randolph P Steel

Donald L LaCroix

David E Atkinson

Tange Nan Barbour

David John Iverson

David V Gangl

Mark David Jaffe

Michael Richard Ouellette

William Vincent Huott

Donald Lawrence Wheater

Leendert M Huisman

Gary William Maier

Mark C Johnson

David E Sweenor

Kathleen G Purdy

Dean G Percy

Kenneth A Lavallee

Thomas P Scanlon

Eric N Smith

Joseph C Pranys

Francois Aube

Timothy M Curtin

A method of testing a device is disclosed. Test data is obtained for a device testing program that tests the device. An adaptation command for testing the device is determined at an adaptive testing engine using obtained test data. The adaptation command is sent from the adaptive testing engine to a tool control application. The tool control application uses the adaptation command to control an operation related to the testing of the device.

Real-time rule engine for adaptive testing of integrated circuits

A method of implementing integrated circuit device testing includes performing baseline testing of a first group of chips using a full set of test patterns, and for chip identified as failing, determining, a score for each test pattern in the full set. The score is indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns. Following the baseline testing, streamlined testing on a second group of chips is performed, using a reduced set of the test patterns having highest average scores as determined by the baseline testing. Following the streamlined testing, full testing on a third group of chips is performed using the full set of test patterns, and updating the average score for each pattern. Further testing alternates between the streamlined testing and the full testing for additional groups of chips.

Integrated circuit test optimization using adaptive test pattern sampling algorithm

A structure has a heat dissipating feature, an internal temperature measurement device, and a memory. The structure generates heat as power is supplied to the structure, and a threshold voltage of the internal temperature measurement device changes as the temperature of the temperature measurement device changes. The embodiments herein establish a linear relationship between temperature and threshold voltage by heating the structure to a first temperature and recording a first threshold voltage, and then heating the structure to a second temperature and recording a second threshold voltage. From this, the embodiments herein calculate a linear relationship between temperature and threshold voltage. Further, the embodiments herein can calculate the temperatures of the structure based only upon the linear relationship and threshold voltages measured from internal temperature measurement device.

Method for monitoring thermal control

An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

Method of adding fabrication monitors to integrated circuit chips

A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.

Designing scan chains with specific parameter sensitivities to identify process defects

A method and system for determining minimum post production test time on an integrated circuit device to achieve optimal reliability of that device utilizing defect counts. The number of defective cells or active elements with defective cells (DEFECTS) on the integrated circuit device are counted and this count serves as a basis for determining the minimum test time. A higher number of DEFECTS results in longer post production testing in order to achieve optimum reliability of the integrated circuit device. The number of DEFECTS can be counted on a device internal to the integrated circuit device and made available to determine the minimum required test time. The number of DEFECTS can also be obtained external to the integrated circuit device by intercepting information routed to another device. Information provided internally and externally can also reveal the physical location of DEFECTS to further refine the minimum required test time.

Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability

A circuit and a method for monitoring defects in an integrated circuit chip. The circuit including a defect monitor portion and a sense element portion, the defect monitor portion either coupled to inputs of sense elements arranged in a chain or coupled between sense elements and forming portions of the chain.

Circuit and method for monitoring defects

A test apparatus and a method for testing an integrated circuit's data storage device's input/output signal pins for alternating current (AC) defects, by providing an interface that will couple each respective individual test contact, in a subset of said contacts, to a select plurality of the data storage input/output signal pins so that when a selected data string is introduced into the integrated circuit so that each input/output pin on a data storage device in the integrated circuit will be tested in sequence whereby the number of contacts required by the tester can be reduced.

Signal pin tester for AC defects in integrated circuits

A statistical method is described for reliability selection of dies on semiconductor wafers using critical wafer yield parameters. This is combined with other data from the wafer or module level reliability screens (such as voltage screen or burn-in) to obtain the relative latent defect density. Finally the modeled results are compared with actual results to demonstrate confidence in the model.

Method of statistical binning for reliability selection

A built-in self-test (BIST) system and method for testing an array of embedded electronic devices, the BIST comprising: a shift register device connected to an output pin of an embedded array of electronic devices being tested and for receiving a failure indication signal at a real-time output pin of the device under test, the shift register generating a unique signature in response to receipt of the failure indication; a device for determining whether the generated unique signature is represented in a table comprising known signature values and corresponding bitmaps of prior determined array defects for that device under test; wherein the need to bitmap the array is avoided when a known failure signature is determined.

System and method to predetermine a bitmap of a self-tested embedded array

A method for determining common failure modes of an integrated circuit device under test is disclosed. In an exemplary embodiment of the invention, a test pattern is applied to a series of inputs of the device under test. A set of output data generated by the device under test is then compared to a set of expected data, with the set of output data being generated by the device under test in response to the test pattern. It is then determined whether the set of output data has passed the test, with the set of output data passing the test if the set of output data matches the set of expected data. If the set of output data has not passed the test, then it is determined whether an output signature corresponding to the set of output data matches a previously stored output signature. Fail data corresponding to the output signature is then stored if the output signature matches a previously stored output signature.

Method and system for determining common failure modes for integrated circuits

Growing community of inventors

Burlington, VT, United States of America

Matthew Sean Grady