Qualcomm Incorporated

Rainbow Technologies, Inc.

Matthew Scott McGregor

Rosario Cammarota

Yucong Tao

Kris Tiri

Nicolas Thaddee Courtois

Tanya Mahajan

Gur Prasad Srivastava

Indranil Banerjee

Thuan P Le

Data blocks of an input data unit may be received in parallel as a data segment on a data bus. For each received data segment, tweak values corresponding to the data blocks may be generated using a key and an input vector. The data blocks may be encrypted using parallel encryption circuitry blocks, based on a symmetric block cipher that uses another key and one of the tweak values. The encrypted data blocks may be combined into an output data unit.

Encryption with enhanced tweak generation

Techniques for mitigating side-channel attacks on cryptographic algorithms are provided. An example method according to these techniques includes applying a block cipher algorithm to an input data to generate a cryptographic output, such that applying the block cipher to input data comprises modifying an output of a stage of the block cipher algorithm such that each output of the stage of the block cipher algorithm has a constant Hamming weight, and outputting the cryptographic output.

Lightweight mitigation against first-order probing side-channel attacks on block ciphers

Disclosed is a method for detecting clock tampering. In the method a plurality of resettable delay line segments are provided. Resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a resettable delay line segment associated with a maximum delay time are each associated with discretely increasing delay times. A monotone signal is provided during a clock evaluate time period associated with a clock. The monotone signal is delayed using each of the plurality of resettable delay line segments to generate a respective plurality of delayed monotone signals. The clock is used to trigger an evaluate circuit that uses the plurality of delayed monotone signals to detect a clock fault.

Apparatus and method for detecting clock tampering

A computationally efficient multiplication method and apparatus for modular exponentiation. The apparatus uses a preload register, coupled to a multiplier at a second input port via a KN bit bus to load the value of the &ldquo;a&rdquo; multiplicand in the multiplier in a single clock pulse. The &ldquo;b&rdquo; multiplicand (which is also KN bits long) is supplied to the multiplier N bits at a time from a memory output port via an N bit bus coupled to a multiplier first input port. The multiplier multiplies the N bits of the &ldquo;b&rdquo; multiplicand by the KN bits of the &ldquo;a&rdquo; multiplicand and provides that product at a multiplier output N bits at a time, where it can be supplied to the memory via a memory input port.

Computationally efficient modular multiplication method and apparatus

A method and apparatus for performing high-speed computation of a Montgomery value defined as 2,mod(n) for an arbitrary modulus n is disclosed. After loading the value of 2,into a first register and the value of the modulus n in a second register, the bits of modulus n are shifted in a most significant bit direction before a repeated modular reduction and squaring process. This allows the computation of the Montgomery value for modulus values of arbitrary sizes while reducing the number of computations required by a processor with a limited operand size.

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Huntington Beach, CA, United States of America

Matthew Scott McGregor