Aeroflex Colorado Springs Inc.

Lsi Logic Corporation

Hyundai Electronics America, Inc.

At&t Global Information Solutions Company

Symbios Logic Inc.

Matthew S Von Thun

Richard K Cole

James P Yakura

Derryl D Allman

Brian E Burdick

Jonathan Mabra

Crystal J Hass

Scott Popelar

Richard Jadomski

Karen Jackson

Scott C Savage

Edson Wayne Porter

Christopher Mnich

George Ott

Scott J Rittenhouse

Brad S Tollerud

An integrated circuit shielding technique utilizing stacked die technology incorporating top and bottom nickel-iron alloy shields having a low coefficient of thermal expansion of especial utility in conjunction with magnetoresistive random access memory (MRAM) and other devices requiring magnetic shielding.

Integrated circuit shielding technique utilizing stacked die technology incorporating top and bottom nickel-iron alloy shields having a low coefficient of thermal expansion

A method of incorporating active error correction inside a memory device is used, whereby memory scrub cycles can be completely hidden from an end user. The method simplifies the design of the memory interface and simplifies the data integrity management unit for the end user. An arbitration unit is implemented to allow concurrent processing of primary (user) and secondary (scrub) requests. The arbitration unit is location aware in context to the primary interface and is responsible for eliminating overlapping memory requests.

Method for concurrent system management and error detection and correction requests in integrated circuits through location aware avoidance logic

A data memory is organized as a logical matrix having multiple virtual data words. Along with the physical representation of the data as being associated with physical memory cells, other virtual data words and their virtual check bits are formed that intersect (logically) with the real data word in a multi-dimensional array. Each of these virtual words can possess errors that can be quickly corrected using independent EDAC methodology. The validity of the virtual word can be used to verify the validity of a single bit in the real word thus correcting multiple bit errors.

Independent orthogonal error correction and detection

A simple voltage detection circuit has few circuit elements, but provides a voltage output that is substantially temperature insensitive. The voltage detection circuit includes a diode-connected transistor, a cascode-connected transistor, as well as first and second resistors coupled between ground and a ramped power supply voltage. The diode-connected transistor exhibits a negative temperature coefficient. The on resistance of the cascode-connected transistor increases with temperature and thus the voltage dropped across the cascode-connected transistor also increases with temperature. By correctly sizing the cascode-connected device, the negative and positive temperature coefficients of the diode-connected and cascode-connected devices can be substantially cancelled out.

Temperature insensitive reference circuit for use in a voltage detection circuit

A delay line appropriate for use in a POR circuit or other integrated circuit in a space environment combines three separate circuit techniques to improve performance without unnecessarily increasing circuit area or adding to manufacturing costs when compared to a simple inverter delay line. The delay line of the present invention uses the selective placement of capacitors throughout the delay line, one-sided current starving, and the incorporation of one-sided Schmitt trigger circuits. Performance of the delay line is substantially immune to SEGR events ('Single Event Gate Rupture') and SET events ('Single Event Transients'). Spurious signals produced by SEGR and SET events are quickly and substantially attenuated.

SET and SEGR resistant delay cell and delay line for Power-On Reset circuit applications

A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an exclusive-OR gate, which controls gating circuitry. The gating circuitry can be a controlled pass-gate circuit and a data latch, an adjustable threshold comparator, or two controlled latches. Transient pulse suppression is achieved with less circuitry and expense than is found in TMR circuits.

Radiation hardened logic circuit

An apparatus comprising a device and a resistor. The device generally comprises (i) a gate configured to receive an input voltage, (ii) a drain coupled to a first supply voltage, and (iii) a source coupled to an output. The resistive element is generally coupled between the source and a second supply voltage. The apparatus generally provides voltage tolerance between the input voltage and the output.

Five volt tolerant and fail safe input scheme using source follower configuration

An apparatus comprising (i) an input circuit configured to provide a predetermined voltage tolerance in response to a plurality of control signals and (ii) a control circuit configured to generate the plurality of control signals in response to one or more input signals.

Five volt tolerant input scheme using a switched CMOS pass gate

An apparatus having a plurality of serially cascaded delay cells each configured to generate a phase of a multi-phase signal and an intermediate signal, where (i) each of the delay cells is generally configured to respond to a bias signal and one of the intermediate signals and (ii) a first of the delay cells is generally configured to respond to an input signal.

Multi-phase edge rate control for SCSI LVD

An integrated inductor is formed on an integrated circuit or other substrate. The inductor is formed of a stack of almost totally enclosed rings of conductive material in which each ring has a single gap. Vias connect adjacent rings on opposite sides of their gaps so as to form a coil shaped structure. The inductor has applications in filtering, in an oscillator, in an antenna, combined with an active detection circuit, combined with an electron source, in a microelectromechanial systems or MEMS, or the like. The inductor may be formed in a vertical orientation or in a horizontal orientation. Chemical mechanical polishing may be used for planarizing layers.

Integrated inductor in semiconductor manufacturing

An improved wafer scale integrated circuit is described which includes non-contact power and data transmission coupling. Wireless power and data coupling reduces the mechanical stresses and strains on the wafer, and makes better use of the wafer area. An additional benefit comes from allowing better heat transfer management. In one embodiment, power is provided by inductive coupling. Data flow into and out of the wafer is accomplished optically, using optical detectors to receive and light emitting diodes to transmit. Multiple devices are integrated onto the semiconductor wafer. Systems may be incorporated using the traditional die sites. Connections between systems are made in the space between die sites.

Method and apparatus for a wafer level system

A method and structure for sensing data such as temperature with respect to objects such as silicon wafers undergoing fabrication or other processes involve the use of a monitor element of material and configuration similar to that of the objects being processed. A structure such as a closed loop or segment of a spiral may be formed on the surface of the monitor element, and acts as a secondary coil when brought into operative relation with a transformer structure which includes a primary coil, a current source and a sensing device. The sensing device senses variations in the electrical characteristics in the primary coil, caused by the presence of the monitor element, and can thereby determine the temperature or other desired data relating to the monitor element, which is substantially the same as comparable data for the objects being processed.

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Colorado Springs, CO, United States of America

Matthew S Von Thun