Micron Technology Incorporated

Lam Research Corporation

Novellus Systems Incorporated

Matthew S Thorum

Gurtej S Sandhu

Steven T Mayer

Shyam Surthi

David W Porter

Haiying Fu

Lee J Brogan

Kunal Shrotri

Byeung Chul Kim

Cornel Bozdog

Joseph Richardson

Michael E Koltonski

Abhilasha Bhardwaj

David H Wells

Jonathan David Reid

Richard J Hill

Collin Howder

Shantinath Ghongadi

Umberto Maria Meotto

Frederick Dean Wilmot

Mark J Willey

Tighe A Spurlin

Robert Marshall Stowell

James E Duncan

Ludan Huang

Charles Lorenzo Merrill

Hyosang S Lee

The present disclosure includes apparatuses and methods related to sublimation in forming a semiconductor. In an example, a method may include forming a sacrificial material in an opening of a structure, wherein the sacrificial material displaces a solvent used in a wet clean operation and removing the sacrificial material via sublimation by exposing the sacrificial material to sub-atmospheric pressure.

Sublimation in forming a semiconductor

Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions include conductive structures. The conductive structures have a first thickness. The proximal regions include insulative structures. The insulative structures have a second thickness at least about as large as the first thickness. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

Microelectronic devices including staircase structures, and related memory devices, electronic systems, and methods

Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

In an example, a method may include removing a material from a structure to form an opening in the structure, exposing a residue, resulting from removing the material, to an alcohol gas to form a volatile compound, and removing the volatile compound by vaporization. The structure may be used in semiconductor devices, such as memory devices.

Residue removal during semiconductor device formation

In an example, a method may include closing an opening in a structure with a sacrificial material at a first processing tool, moving the structure from the first processing tool to a second processing tool while the opening is closed, and removing the sacrificial material at the second processing tool. The structure may be used in semiconductor devices, such as memory devices.

Using sacrificial solids in semiconductor processing

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The second tiers comprise doped silicon dioxide and the first tiers comprise a material other than doped silicon dioxide. The stack comprises laterally-spaced memory-block regions. Channel-material-string constructions extend through the first tiers and the second tiers in the memory-block regions. The doped silicon dioxide that is in the second tiers is etched selectively relative to said other material that is in the first tiers and selectively relative to and to expose an undoped silicon dioxide-comprising string of a charge-blocking material that is part of individual of the channel-material-string constructions. Structure independent of method is disclosed.

Integrated circuitry, a method used in forming integrated circuitry, and a method used in forming a memory array comprising strings of memory cells

The present disclosure includes apparatuses and methods related to freezing a sacrificial material in forming a semiconductor. In an example, a method may include solidifying, via freezing, a sacrificial material in an opening of a structure, wherein the sacrificial material has a freezing point below a boiling point of a solvent used in a wet clean operation and removing the sacrificial material via sublimation by exposing the sacrificial material to a particular temperature range.

Freezing a sacrificial material in forming a semiconductor

Gas residue removal

Removing a sacrificial material via sublimation in forming a semiconductor

Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

Integrated circuitry comprising an array, method of forming an array, method of forming DRAM circuitry, and method used in the fabrication of integrated circuitry

An example of forming semiconductor devices can include forming a silicon-hydrogen (Si&#x2014;H) terminated surface on a silicon structure that includes patterned features by exposing the silicon structure to a hydrogen fluoride (HF) containing solution and performing a surface modification via hydrosilylation by exposing the Si&#x2014;H terminated surface to an alkene and/or an alkyne.

Hydrosilylation in semiconductor processing

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Boise, ID, United States of America

Matthew S Thorum