Intel Corporation

Matthew S Jones

Morteza Cyrus Afghahi

Babak B Nikjou

A serial-deserializer converts a high speed serial data input to a lower speed parallel output. By including this circuit on a chip, connections to the chip are made more easily. A gated voltage controlled oscillator provides clock signals to sample the data input at a high rate. The output signals are thus provided at a slower rate.

High speed serial-deserializer receiver

An apparatus comprising a first circuit configured to receive a first clock signal and delaying the first clock signal by a first delay to generate a second clock signal, the first delay being a first function of a first signal; a phase-frequency detector configured to receive the first clock signal and the second clock signal and generate a second signal dependent on the first delay; a second circuit configured to receive tile second signal and generate a third signal, the third signal being a digital signal; and a current mirror configured to generate the first signal, the first signal being a second function of the third signal.

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Chandler, AZ, United States of America

Matthew S Jones