Lsi Logic Corporation

Matthew Russell

Todd A Randazzo

Kenneth Stanley Szajda

Jonathan Alois Schmitt

Kenneth G Richardson

Scott C Savage

Edson Wayne Porter

Hoang P Nguyen

Toan Dinh Nguyen

Timothy McGonagle

Dushyant Narayen

Dongyi Zhou

A bus layout design is provided which includes a first electrically conductive layer with a first bus and a second bus and a second electrically conductive layer with a first bus and a second bus. Vias are provided between the first electrically conductive layer and the second electrically conductive layer such that the first bus and the second bus of the first electrically conductive layer are electrically connected.

Multi-layer staggered power bus layout design

A level shifter circuit configured for use between a core of a chip and input/output transistor of the chip in order to shield low voltage devices residing on the core. The level shifter circuit includes voltage tolerant native devices which have VDDCORE on their gates, and each voltage tolerant native device is cascoded with a low voltage transistor on the core.

CMOS level shifters using native devices

A power-on reset circuit is provided, which includes a ground input, a power input having a voltage relative to the ground input, a reset output, a self-initializing latch, a high voltage trigger circuit and a discharge circuit. The self-initializing latch has first and second latch nodes which are initialized to logic high and low states, respectively, upon initial application of power to the power input. One of the first and second latch nodes is coupled to the reset output. The high voltage trigger circuit is coupled to the first latch node and reverses the states of the first and second latch nodes when the voltage rises above a high trigger voltage. The discharge circuit is coupled to the second latch node and has a switch circuit, which selectively couples the second latch node to the ground input when the voltage falls below a low trigger voltage.

Power-on reset circuit

An integrated circuit having input output buffers, where the integrated circuit is powered by at least a core power supply and an input output power supply. A level shifter receives an active low signal that indicates that the core power supply has powered down. The level shifter then outputs a known state upon receipt of the active low signal. A control circuit receives the known state form the level shifter, and then tristates the input output buffers upon receipt of the known state.

Control circuit for power

An open drain driver circuit includes first and second NMOS driver transistors, a delay circuit, an OR gate and an AND gate. Each NMOS driver transistor has a drain coupled to an output terminal, a source coupled to a supply terminal, and a gate. The delay circuit has an input coupled to the input terminal and has an output. The OR gate has a first input coupled to the input terminal, a second input coupled to the output of the delay circuit and an output coupled to the gate of the first NMOS transistor. The AND gate has a first input coupled to the input terminal, a second input coupled to the output of the delay circuit and an output coupled to the gate of the second NMOS transistor.

Growing community of inventors

Burnsville, MN, United States of America

Matthew Russell