International Business Machines Corporation

Other

Globalfoundries Inc.

Matthew Roger Ellavsky

Timothy D Helvey

Sean T Evans

Bradley Craig White

Alan G Gara

Martin Ohmacht

Thomas M Gooding

Rudolf Adriaan Haring

Phillip P Normand, Ii

Jason L Van Vreede

Dong Chen

Mark Edwin Giampapa

Gerard Vincent Kopcsay

Ralph E Bellofatto

Michael K Gschwind

Valentina Salapura

Paul William Coteus

Michael A Blocksome

Joseph D Ratterman

Philip Heidelberger

Adam James Muff

Todd Edward Takken

Bruce Martin Fleischer

Alexandre E Eichenberger

Robert William Wisniewski

John A Gunnels

Burkhard Steinmacher-Burow

Kathryn Mary O'Brien

Mark Gregory Megerian

Matthias Augustin Blumrich

Sameh W Asaad

Shawn Anthony Hall

Thomas Winters Fox

John Kevin O'Brien

Chen-Yong Cher

Barry Marshall Trager

Peng Wu

Charles David Wait

Sameer Kumar

James Anthony Marcella

Todd Alan Inglett

George L Chiu

Krishnan Sugavanam

Jeffrey John Parker

Robert Matthew Senger

Noel A Eisley

David L Satterfield

Douglas R Miller

Craig Brian Stunkel

Amith R Mamidala

Yutaka Sugawara

Kristan D Davis

Jose R Brunheroto

Michael B Mundy

Robert E Walkup

James Lee Van Oosten

Samuel J Miller

Ruth Janine Poole

Gabor J Dozsa

Peter Boyle

Brant L Knudson

Norman Christ

Kahn C Evans

Brandon Edward Schenck

William Maupin Stockdell

Alfred Thomas Watson, Iii

Brian E Smith

Steven Michael Douskey

Anthony Gus Aipperspach

Mark James Jeanson

Kent Harold Haselhorst

Scott Michael Willenborg

Kerry Christopher Imming

Aj KleinOsowski

Don Darrell Reed

Richard A Swetz

Thomas A Liebsch

Morgan D Davis

Daniel J Littrell

Lance G Hehenberger

Richard S Little

Mark G Veldhuizen

Jason L VanVreede

Ross L Franke

Michael Nordquist

Gregory P Snyder

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

A method, system and computer program product are provided for implementing enhanced net routing for congestion resolution of non-rectangular or rectangular hierarchical macro designs of an integrated circuit chip. Congested macro nets near a macro boundary are identified. Wiring channels are reserved outside the macro boundary, allowing congested macro nets to be routed outside the physical boundary of the macro while still being logically contained within the macro.

Implementing enhanced net routing congestion resolution of non-rectangular or rectangular hierarchical macros

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

A method, system and computer program product are provided for implementing an enhanced Z-directional macro port assignment or three-dimensional port creation for random logic macros of heterogeneous hierarchical integrated circuit chips. An initial port placement is provided on a layer for a macro. The initial port placement is expanded to provide a three-dimensional port shape including a plurality of metal layers along a z-axis. Wire routing of each of the macro level and a chip top level is defined within the expanded three-dimensional port shape. Each unnecessary metal layer of the expanded three-dimensional port shape is removed, providing a final three-dimensional port shape.

Implementing Z directional macro port assignment

In an embodiment, a buffer bay is represented with a moveable object that has a location within a unit in a netlist. The location of the moveable object that represents the buffer bay is changed to a new location in the netlist if changing the location improves placement within the unit. In an embodiment, a net weight of a net that connects the moveable object to an artificial pin is considered in determining whether to change the location to the new location. In an embodiment a bounding area that encompasses the location is considered in determining whether to change the location to the new location.

Changing the location of a buffer bay in a netlist

A method and elastic buffer circuit are provided for implementing low power, single master-slave elastic buffers in a network chip design to provide a continuous stream of data to multiple sinks from multiple sources, and a design structure on which the subject circuit resides. An elastic buffer only uses a single master-slave register. The circuit includes a finite state machine, and a latch control block (LCB) to implement the single master-slave elastic buffer removing all &#xbd; cycle paths between buffer locations enabling usage of the single master-slave register.

Implementing low power, single master-slave elastic buffer

A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

Global synchronization of parallel processors using clock pulse width modulation

A method for designing integrated circuits uses clock signal interleaving to reduce the likelihood of a soft error arising from an upset in a clock distribution network. At least two circuits in a circuit description are identified as being sensitive to radiation, and different clock distribution nodes are assigned to the two circuits. Several exemplary implementations are disclosed. The second circuit may be a redundant replica of the first circuit, such as a reset circuit. The first and second circuits may be components of a modular redundant circuit such as a triple modular redundancy flip-flop. The first circuit may include a set of data bits for an entry of a storage array such as a register or memory array, and the second circuit may include a set of check bits associated with the entry.

Radiation tolerance by clock signal interleaving

An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan

A novel clock splitter that has a local internal clock frequency-divider is presented. The clock splitter comprises an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider, wherein the clock frequency-divider selectively suppresses clock pulses in the C clock to generate a slower C clock signal that is slower than the oscillator clock; and a B/C clock order logic, wherein the B/C clock order logic phase shifts the C clock relative to a B clock. The clock frequency-divider may selectively suppress pulses in the B clock to generate a slower B clock signal. The slower B and C clock signals may have a same or different frequency. In one embodiment, the clock splitter is located at a terminal leaf of a clock tree.

High-speed leaf clock frequency-divider/splitter

A training shoe for soccer includes a pressure-responsive sensor mounted with respect to a soccer shoe at a selected location, for example at the instep or along the laces at the top of the shoe. When a soccer ball is kicked at the selected location, the sensor provides an electrical signal to a microprocessor, causing selection logic in the microprocessor to choose one of several control words. The selected control word is provided to a voice playback circuit to select one of several digital data sets, each set corresponding to a different sound. The playback circuit provides an analog electrical control signal to a speaker, thereby generating a selected sound corresponding to the selected digital data set. System components can be mounted permanently to a shoe, or to a cover or strap arrangement releasably mounted to the shoe.

Training shoe for soccer

Growing community of inventors

Rochester, MN, United States of America

Matthew Roger Ellavsky