International Business Machines Corporation

Microsoft Technology Licensing, LLC

Globalfoundries Inc.

Matthew Ray Tubbs

Adam James Muff

Robert Allen Shearer

Paul E Schardt

Eric Oliver Mejdrich

Charles David Wait

Mark Joseph Hickey

Ryan Scott Haraden

Stephen Joseph Schwinn

Gordon Clyde Fossum

Miguel Comparan

Ashish Gupta

Sherman Matthew Dance

Rob Shearer

Andrew Patrick Freemyer

A method and circuit arrangement for selectively predicating an instruction in an instruction stream based upon a value corresponding to a predication register address indicated by a portion of an operand associated with the instruction. A first compare instruction in an instruction stream stores a compare result in at a register address of a predication register. The register address of the predication register is stored in a portion of an operand associated with a second instruction, and during decoding the second instruction, the predication register is accessed to determine a value stored at the register address of the predication register, and the second instruction is selectively predicated based on the value stored at the register address of the predication register.

Instruction predication using unused datapath facilities

This document relates to power consumption of computing devices. One example is a face detection circuit that includes a camera interface, a processing component, and a power management interface. The camera interface can be configured to communicate with a camera. The processing component can be configured to instruct the camera to provide image data at multiple levels of resolution, and perform multiple stages of analysis on the image data obtained from the camera to detect the presence of a face in the image data. The power management interface can be configured to output an indication when the face is detected in the image data.

Face detection circuit

A method and circuit arrangement utilize inactive non-pipelined operation resources in one processing core of a multi-core processing unit to execute non-pipelined instructions on behalf of another processing core in the same processing unit. Adjacent processing cores in a processing unit may be coupled together such that, for example, when one processing core's non-pipelined execution sequencer is busy, that processing core may issue into another processing core's non-pipelined execution sequencer if that other processing core's non-pipelined execution sequencer is idle, thereby providing intermittent concurrent execution of multiple non-pipelined instructions within each individual processing core.

Concurrent multiple instruction issued of non-pipelined instructions using non-pipelined operation resources in another processing core

Methods, apparatus, and computer-readable storage media are disclosed for applying filtering operations to data transferred as part of a direct memory access (DMA) operation. In one example of the disclosed technology, a system includes a processor, memory, and a direct memory access (DMA) engine coupled to the memory for reading a set of data from a selected range of read memory addresses for the memory without using the processor. A line buffer coupled to the DMA engine is configured to receive DMA read data and temporarily store a portion, but not all of the data set being read by the DMA engine in a line buffer. A digital filter is configured to apply a filtering operation to a windowed subset of the buffered portion of the data set, producing filtered data that is stored to a selected range of write memory addresses for the memory, without using the processor.

Direct memory access with filtering

A particular method includes receiving, at a processor, an instruction and an address of the instruction. The method also includes preventing execution of the instruction based at least in part on determining that the address is within a range of addresses.

Instruction predication using instruction address pattern matching

Methods for preprocessing pixel data using a Direct Memory Access (DMA) engine during a data transfer of the pixel data from a first memory (e.g., a DRAM) to a second memory (e.g., an SRAM) are described. The pixel data may derive from a color camera or a depth camera in which individual pixel values are not a multiple of eight bits. In some cases, the DMA engine may perform a variety of image processing operations on the pixel data prior to the pixel data being written into the second memory. In one embodiment, the DMA engine may be configured to determine whether one or more pixels corresponding with the pixel data may be invalidated or skipped based on a minimum pixel value threshold and a maximum pixel value threshold and to embed pixel skipping information within unused bits of the pixel data.

Low power DMA snoop and skip

Embodiments are disclosed for a method of executing instructions in a processing core of a microprocessor. In one embodiment, the method comprises, in a first clock domain, receiving an input from a second clock domain external to the first clock domain, the input comprising an indication from the second clock domain regarding whether to execute an instruction in the first clock domain. The method further comprises synchronizing the input from the second clock domain with the first clock domain, if the instruction is a predicatable instruction and the indication matches a predicate condition that indicates not to perform the instruction, then not performing the instruction, and otherwise performing the instruction.

Control of predication across clock domains

A method maintains power usage prediction information for one or more functional units in branch prediction logic for a processing unit such that the power consumption of a functional unit may be selectively reduced in association with the execution of branch instructions when it is predicted that the functional unit will be idle subsequent to the execution of such branch instructions.

Branch prediction with power usage prediction and control

A circuit arrangement maintains power usage prediction information for one or more functional units in branch prediction logic for a processing unit such that the power consumption of a functional unit may be selectively reduced in association with the execution of branch instructions when it is predicted that the functional unit will be idle subsequent to the execution of such branch instructions.

A digital signal processor includes a variable precision hardware pipeline that provides a maximum level of precision using a first plurality of bits for a mathematical representation. The pipeline stages include data registers to store the first plurality of bits. A precision select module selects a level of precision for processing a block of instructions and sets a precision control register. Logic circuitry utilizes the precision control register to gate the clock signal for one or more of the first plurality of bits to reduce the precision of the hardware pipeline. The logic circuitry disables the clock signal for the data latches in the pipeline corresponding to bits to be disabled to reduce the precision. By disabling the clock signal for the data registers, the amount of power consumed by the pipeline can be reduced.

Variable precision in hardware pipelines for power conservation

Various methods tightly couple together decode logic associated with multiple types of execution units and having varying priorities to enable instructions that are decoded as valid instructions for multiple types of execution units to be forwarded to a highest priority type of execution unit among the multiple types of execution units. Among other benefits, when an auxiliary execution unit is coupled to a general purpose processing core with the decode logic for the auxiliary execution unit tightly coupled with the decode logic for the general purpose processing core, the auxiliary execution unit may be used to effectively overlay new functionality for an existing instruction that is normally executed by the general purpose processing core, e.g., to patch a design flaw in the general purpose processing core or to provide improved performance for specialized applications.

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Methods for preprocessing pixel data using a Direct Memory Access (DMA) engine during a data transfer of the pixel data from a first memory (e.g., a DRAM) to a second memory (e.g., a local cache) are described. The pixel data may derive from an image capturing device (e.g., a color camera or a depth camera) in which individual pixel values are not a multiple of eight bits. In some embodiments, the DMA engine may perform a variety of image processing operations on the pixel data prior to the pixel data being written into the second memory. In one example, the DMA engine may be configured to identify and label one or more pixels as being within a particular range of pixel values and/or the DMA engine may be configured to label pixels as belonging to one or more pixel groups based on their pixel values.

Low power DMA labeling

A method and circuit arrangement selectively perform regular expression matching in connection with accessing data with a processing unit based upon one or more regular expression matching-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A regular expression matching-related attribute in such a data structure may be used to control whether data being communicated between the processing unit and a communications bus is routed through an expression engine integrated with the processing unit such that regular expression matching may be performed in association with the data communication.

Regular expression memory region with integrated regular expression engine

A circuit arrangement decodes instructions based in part on one or more decode-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a decode of an instruction stored in a page of memory, such that one or more attributes associated with the page in the data structure may be used to control how that instruction is decoded.

Instruction set architecture with opcode lookup using memory attribute

A method decodes instructions based in part on one or more decode-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a decode of an instruction stored in a page of memory, such that one or more attributes associated with the page in the data structure may be used to control how that instruction is decoded.

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Rochester, MN, United States of America

Matthew Ray Tubbs