International Business Machines Corporation

Other

Matthew R Wordeman

Jack Allan Mandelman

Lia Krusin-Elbaum

Dennis Merton Newns

Toshiaki Kirihata

Albert M Young

Louis L Hsu

Joel Abraham Silberman

John Kenneth DeBrosse

Stephen A Parke

Sang Hoo Dhong

Paul Christian Parries

Richard Michael Parent

John Edward Barth, Jr

William Robert Reohr

John Anthony Bracchitta

Jeffrey P Gambino

Chung H Lam

William R Tonti

Leland Chang

Ching-Hsiang Hsu

Edmund Juris Sprogis

Wei Hwang

Anna Wanda Topol

Bruce Kenneth Furman

Cornelia K Tsang

Kuan-Neng Chen

Bruce Gordon Elmegreen

Gregory J Fredeman

Mark A Jaso

Louis L C Hsu

Liang-Teck Pang

Mark David Jacunski

Lewis M Terman

Oliver Weinfurtner

Michael R Scheuermann

Alexandre Acovic

Being S Wu

Rajiv V Joshi

Daniel Christopher Worledge

Arvind Kumar

Louis Lu-Chen Hsu

Robert H Dennard

Li-Kong Wang

Hussein Ibrahim Hanafi

Richard Joseph Gambino

Praveen Chaudhari

Kevin William Gorman

Thomas M Maffitt

Robert B Laibowitz

Hing Wong

Roger Hilsen Koch

Donald J Samuels

Hwa-Joon Oh

Hoki Kim

George A Sai-Halasz

Shih-Hsien Lo

Yuan-Chen Sun

Alan D Norris

Jonathan R Fales

John E Barth

Michael P Beakes

Kotb Jabeur

Eti Ganin

Hans-Oliver Joachim

A dynamic redundancy memory includes a redundancy control module and an ECC module. The ECC detects bit errors, stores the addresses of the error bits, counts the bit errors. If the number of errors exceeds a threshold, the ECC identifies the address as a suspect bit and sends a suspect bit signal to the redundancy control module, which determines whether the suspect bit address is already stored in a redundancy element. If already stored, the element is marked bad, the address of the suspect bit is replaced with a new redundant address and the suspect bit address is stored in a good unused element. The ECC determines whether the error occurrences at the address exceeds a bit error rate threshold. If the error rate threshold is exceeded, the ECC identifies the address as suspect bit and sends the suspect bit signal to the redundancy control module.

Dynamic redundancy for memory

A magnetoresistive random access memory (MRAM) system is described. The system includes a sense amplifier circuit for sensing a data state of an MRAM data cell. The circuit includes a first leg and a second leg, and is configured to perform a two-phase read including a first phase in which a first transistor is coupled to a reference resistance circuitry and a second transistor is coupled to a data resistance circuitry, and a second phase in which the first transistor is coupled to the data resistance circuitry and the second transistor is coupled to the reference resistance circuitry. The circuit further includes a reference trim circuitry and a data trim circuitry configured to correct for device mismatch errors relating to the two-phase read of the sense amplifier circuit. The circuit further includes a comparator circuit configured to output the data state of the data cell.

Trimming MRAM sense amp with offset cancellation

Improved STT MRAM midpoint reference cell configurations are provided. In one aspect, a STT MRAM midpoint reference cell includes: a plurality of word lines having at least one write reference word line and at least one read reference word line; a plurality of bit lines perpendicular to the word lines; at least one source line perpendicular to the bit lines; at least one first magnetic tunnel junction in series with i) a first field effect transistor gated by the write reference word line and ii) a second field effect transistor gated by the read reference word line; and at least one second magnetic tunnel junction in series with iii) a third field effect transistor gated by the write reference word line and iv) a fourth field effect transistor gated by the read reference word line. A method of operating a STT MRAM midpoint reference cell is also provided.

STT MRAM midpoint reference cell allowing full write

There is provided a strata manager within a 3D chip stack having two or more strata. The strata manager includes a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata for storing a set of bits. The set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. Additionally, a stratum identifier within a 3D stack and stack-wide scan circuit within a 3D stack are provided.

Programming the behavior of individual chips or strata in a 3D stack of integrated circuits

An array of contact pads on a semiconductor structure has a pitch less than twice an overlay tolerance of a bonding process employed to vertically stack semiconductor structures. A set of contact pads within the area of overlay variation for a matching contact pin may be electrically connected to an array of programmable contacts such that one programmable contact is connected to each contact pad within the area of overlay variation. One contact pad may be provided with a plurality of programmable contacts. The variability of contacts between contact pins and contact pads is accommodated by connecting or disconnecting programmable contacts after the stacking of semiconductor structures. Since the pitch of the array of contact pins may be less than twice the overlay variation of the bonding process, a high density of interconnections is provided in the vertically stacked structure.

Method of forming adaptive interconnect structure having programmable contacts

A three-terminal switching device for use in integrated circuit devices, including a phase change material (PCM) disposed in contact between a first terminal and a second terminal; a heating device disposed in direct electrical contact between said second terminal and a third terminal, said heating device positioned proximate said PCM, and configured to switch the conductivity of a transformable portion of said PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate said heater from said PCM material, and said heater from said first terminal.

Three-terminal cascade switch for controlling static power consumption in integrated circuits

There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.

3D integrated circuit stack-wide synchronization circuit

There is provided a connection configuration for a multiple layer chip stack having two or more strata. Each of the two or more strata has multiple circuit components, a front-side and a back-side. The connection configuration includes a connection pair having as members a front-side connection and a backside connection unconnected to the front-side connection. The front-side connection and the backside connection are co-located with respect to each other on a given stratum from among the two or more strata, and are respectively connected to different ones of the multiple circuit components on the given stratum. At least one of the front-side connection and the backside connection is also connected to a particular one of the multiple circuit components on an adjacent stratum to the given stratum from among the two or more strata.

Configuration of connections in a 3D stack of integrated circuits

A switching circuit includes a plurality of three-terminal PCM switching devices connected between a voltage supply terminal and a sub-block of logic. Each of the switching devices includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance state and a higher resistance state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.

There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements. The method includes performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack. The method further includes checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack.

3D inter-stratum connectivity robustness

Adaptive interconnect structure

A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

Hermetic seal and reliable bonding structures for 3D applications

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Kula, HI, United States of America

Matthew R Wordeman