Rank Cintel Limited

Matthew R Starr

A plurality n of digital video data streams are individually latched into respective input latches 11.sub.1 to 11.sub.n by a first clock signal LPClk. Two out of n select signals are applied by a selector 16 to enable inputs 14 of the input latches 11.sub.1 to 11.sub.n to select alternate half clock cycles of latched video data and to output such video data to a common bus 19 which supplies two output latches 20 and 21 latched respectively by an antiphase clock signal FLPClk and the signal LPClk so that one of the selected streams is latched into latch 20 as foreground and the other into latch 21 as background. Further latches 31 and 32, and 33 and 34, may be employed to bring the foreground and background streams into relative synchronism.

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Ware, United Kingdom

Matthew R Starr