Apple Inc.

Matthew R Johnson

Vinodh R Cuppu

Nachiappan Chidambaram Nachiappan

Robert E Jeter

Rakesh L Notani

Shingo Suzuki

Pradeep Kanapathipillai

Richard F Russo

John H Kelm

Rajat Goel

Naveen Kumar Korada

Raghava Rao V Denduluri

Alma L Juarez Dominguez

Edvin Catovic

Suhas Kumar Suvarna Ramesh

Pankaj Lnu

Mohammad Rizwan

Systems, apparatuses, and methods for controlling bandwidth through shared transaction limits are described. An apparatus includes at least a plurality of agents, a plurality of transaction-limit (T-Limit) nodes, a T-Limit manager, and one or more endpoints. The T-Limit manager creates a plurality of credits for the plurality of agents to send transactions to a given endpoint. Then, the T-Limit manager partitions the credits into N+1 portions for N agents, wherein the extra N+1 portion is a shared pool for use by agents when they run out of their private credits. The T-Limit manager assigns a separate private portion of the N portions to the N agents for use by only the corresponding agent. When an agent runs out of private credits, the agent's T-Limit node sends a request to the T-Limit manager for credits from the shared pool.

Systems and methods to control bandwidth through shared transaction limits

Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.

Filtering memory calibration

A processor includes an instruction issue circuit, and high-utilization and low-utilization execution unit circuits coupled to execute instructions received from the instruction issue unit. On average, utilization of the low-utilization execution unit circuit is lower than utilization of the high-utilization execution unit circuit. The processor also includes a retention circuit coupled to a different power domain than the low-utilization execution unit circuit, and a power management circuit. The power management circuit may be configured to detect that inactivity of the low-utilization execution unit circuit satisfies a threshold inactivity level; upon detecting that the threshold inactivity level is satisfied, cause architecturally-visible state of the low-utilization execution unit circuit to be copied to the retention circuit; and subsequent to copying of the architecturally-visible state to the retention circuit, cause the low-utilization execution unit circuit to enter a power-off state, where the retention circuit retains stored data during the power-off state.

Execution unit power management

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Newark, CA, United States of America

Matthew R Johnson