Agere Systems Inc.

Lucent Technologies Inc.

Matthew R Henry

Steven E Strauss

William R Bullman

Ryan S Holmqvist

Eugene F Weber

In accordance with exemplary embodiments, a Fast Fourier Transform (FFT) architecture includes elements that perform a radix-2 FFT butterfly in one processor clock cycle at steady state. Some exemplary implementations of the FFT architecture incorporate register and data path elements that relieve memory bandwidth limitations by pairing operands consumed by and results generated by two adjacent butterflies in the overall N-point FFT operation.

Single-cycle FFT butterfly calculator

A method and apparatus for powering digital logic circuits that provides low power consumption while maintaining high performance. The circuit is divided into logic elements necessary for maintaining the state of the circuit and those that are not. The state-maintaining logic uses low-leakage, low performance transistors, and is continually powered. The remainder of the circuit uses standard transistors, i.e., high performance, high-leakage transistors, and is only powered when the circuit is active, i.e., not in a standby mode. Two power rails are used, one for the state maintaining components and one for the non-state-maintaining components. The state-maintaining logic is functionally separated from the remainder of the circuit when the remainder of the circuit is being powered up or down to avoid short-circuiting any elements. Typical state-maintaining components are sequential logic gates. Typical non-state maintaining components are combinational logic gates. A typical functional isolation gates is a NOR gate.

Sequential/combinational logic transistor segregation for standby power and performance optimization

A data-based software type link integrity module is implemented separately in hardware (e.g., using physical gates, using a microcontroller, etc.) and separated from core CPU functionality in a network device, such that the link integrity module may remain powered in a cold power mode (e.g., when core functionality is powered down). The separately powered data-based link integrity module is powered by an auxiliary backup power source. Thus, when in a power down mode (e.g., when in an ACPI defined D3 type cold state) a minimal power source may be used to power the separate link integrity module separate from the power source to the core network device functionality. The separately powered data-based link integrity module may be redundant to a software driver type data-based link integrity module implemented in core memory and enabled or disabled as desired. Alternatively, the separately powered data-based link integrity module may be in lei of the otherwise conventional software driver implemented in core memory and permanently enabled.

Link integrity duality for network devices in cold power state

A translation system and related method for use with a communications device having a physical layer system and a data link layer system with a media access control layer subsystem and coupleable to a communications network. In one embodiment, the translation system includes a generator that constructs a piggyback packet containing characteristics associated with the physical layer system. The translation system also includes a correlator, coupled to the generator, that receives the piggyback packet and extracts information about the physical layer system. The generator and correlator transmit and receive the piggyback packet without substantially modifying the media access control layer subsystem.

Translation system and related method for use with a communication device

A bus master controller comprising a plurality of logic modules, each module coupled to a separate bus driver circuit. The logic module operates using a 'break-before-make' protocol derived from a finite state machine, delay element and exclusive-OR gate. The finite state machine generates a predetermined sequence that requires an 'assert' signal to always be delayed with respect to a 'de-assert' signal, thus eliminating the possibility that more than one set of bus drivers will be coupled to the bus at any one time.

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Fogelsville, PA, United States of America

Matthew R Henry