California Institute of Technology

United States of America As Represented by the Administrator of Nasa

Matthew R Dickie

Michael E Hoenk

Shouleh Nikzad

Todd J Jones

Bedabrata Pain

Frank Greer

Thomas J Cunningham

Bruce R Hancock

Daniel W Wilson

Karl Y Yee

Cecile D Jung-Kubiak

Richard P Vasquez

Richard E Muller

Victor E White

Chao Sun

James E Polk

Kenneth W Newton

Christopher James Wrigley

Colleen M Marrese-Reading

H Frank Greer

John R Anderson

Nima Rouhi

Micro-emitter arrays and methods of microfabricating such emitter arrays are provided. The microfabricated emitter arrays incorporate a plurality of emitters with heights greater than 280 microns with uniformity of +/&#x2212;10 microns arranged on a supporting silicon substrate, each emitter comprising an elongated body extending from the top surface of the substrate and incorporating at least one emitter tip on the distal end of the elongated body thereof. The emitters may be disposed on the substrate in an ordered array in an X by Y grid pattern, wherein X and Y can be any number greater than zero. The micro-emitter arrays may utilize a LMIS propellant source including, for example, gallium, indium, bismuth, or tin. The substrate may incorporate at least one through-via providing a fluid pathway for the LMIS propellant to flow from a propellant reservoir beneath the substrate to the top substrate surface whereupon the micro-emitter array is disposed.

Micro-emitters for electrospray systems

A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.

Sparsely-bonded CMOS hybrid imager

A process for removing indium oxide from indium bumps in a flip-chip structure to reduce contact resistance, by a multi-step plasma treatment. A first plasma treatment of the indium bumps with an argon, methane and hydrogen plasma reduces indium oxide, and a second plasma treatment with an argon and hydrogen plasma removes residual organics. The multi-step plasma process for removing indium oxide from the indium bumps is more effective in reducing the oxide, and yet does not require the use of halogens, does not change the bump morphology, does not attack the bond pad material or under-bump metallization layers, and creates no new mechanisms for open circuits.

Method to improve indium bump bonding via indium oxide removal using a multi-step plasma process

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Altadena, CA, United States of America

Matthew R Dickie