Shenzhen Goodix Technology Co., Ltd.

Silicon Laboratories Inc.

Other

Matthew Powell

Mohamed M Elsayed

Chao Yang

Jinwen Xiao

Scott D Willingham

Xiaodong Wang

Shouli Yan

Gang Yuan

Nicholas Montgomery Atkinson

David R Welland

Axel Thomsen

Kenneth Wilson Fernald

Dazhi Wei

Praveen Kallam

Sudipta Sarkar

Franciscus Petrus Antonius Van Der Velden

Techniques are described for efficient high-resolution output of an image captured using a high-pixel-count image sensor based on pixel binning followed by luminance-guided umsampling. For example, an image sensor array is configured according to a red-green-blue-luminance (RGBL) CFA pattern, such that at least 50-percent of the imaging pixels of the array are luminance (L) pixels. Pixel binning is used during readout of the array to concurrently generate a downsampled RGB capture frame and a downsampled L capture frame. Following the readout, the L capture frame is upsampled (e.g., by upscaling and interpolation) to generate an L guide frame with 100-percent luminance density. An upsampled RGB frame can then be generated by interpolating the RGB capture frame based both on known neighboring RGB information (e.g., from the RGB capture frame and previously interpolated information), as adjusted based on local luminance information from the L guide frame.

High-resolution image capture by luminance-driven upsampling of pixel-binned image sensor array output

An image sensor includes ADCs, each including a comparator receiving a ramp signal and an image signal, and generating a comparator output. Each ADC also includes a counter ceasing to change a digital count value in response to a change in the comparator output. The digital count value has a first resolution. Each ADC also includes a delay line circuit including a delay line generating a first digital value encoding a duration of a period of the counter clock and generating a second digital value encoding a first portion of the period of the counter clock. Each ADC also includes a delay to digital circuit generating a digital output value based on the first and digital values. The digital output value encodes a second value of the ramp signal, where the digital count value has a second resolution that is greater than the first resolution.

Image sensor having high resolution analog to digital converter

Techniques are described for disparity-preserving pixel binning during consistently binned parallel readout of an imaging sensor array having both phase detection autofocus (PDAF) pixels and imaging pixels. Each group of PDAF pixels and each group of imaging pixels is coupled with pixel actuators according to an particular arrangement, so that consistently applied control of the pixel actuators results in desired binning of both the PDAF pixels and the imaging pixels. According to some implementations, though such control of the pixel actuators is consistently applied across the pixels of the array, parallel readout of the sensor array yields diagonally binned imaging pixels, but vertically binned PDAF pixels to preserve horizontal PDAF disparity information. Additionally or alternatively, disparity-inducing structures are configured to position same-disparity PDAF pixels so that consistently applied control of the pixel actuators preserves disparity information during binning.

Disparity-preserving binning for phase detection autofocus in digital imaging systems

Techniques are described for efficient staggered high-dynamic-range (HDR) output of an image captured using a high-pixel-count image sensor based on pixel binning followed by luminance-guided upsampling. For example, an image sensor array is configured according to a red-green-blue-luminance (RGBL) CFA pattern, such that at least 50-percent of the imaging pixels of the array are luminance (L) pixels. In each image capture time window, multiple (e.g., three) luminance-enhanced (LE) component images are generated. Each LE component image is generated by exposing the image sensor to incident illumination for a respective amount of time, using pixel binning during readout to generate appreciably downsampled color and luminance capture frames, generating an upsampled luminance guide frame from the luminance capture frame, and using the upsampled luminance guide frame to guide upsampling (e.g., and remosaicking) of the color capture frame. The resulting LE components images can be digitally combined to generate an HDR output image.

Staggered high-dynamic-range image capture with luminance-driven upsampling of pixel-binned image sensor array output

An image sensor includes a pixel array comprising a plurality of pixels, a color filter array comprising a plurality of color filter clusters overlying the pixel array, and readout circuitry configured to concurrently provide the pixels sharing the common filter cluster and having a first exposure time to a readout line for digital data conversion. Each of the color filter clusters includes a group of same color filters, and pixels sharing a common color filter cluster have different exposure times.

Partial pixel binning for CIS

An image sensor includes a pixel array having a plurality pixels arranged in a plurality of pixel clusters coupled to a plurality of column busses, a plurality of voltage supplies coupled to the plurality of pixel clusters, and ping-pong readout circuitry. Pixel clusters in adjacent column busses are supplied with different voltage supplies. The ping-pong readout circuitry includes multiplexing circuitry coupled to the plurality of column busses, and a plurality of analog-to-digital converters coupled to the multiplexing circuitry. The image sensor also includes a controller configured to selectively couple a pixel signal of a pixel cluster to a column bus to an ADC for signal conversion.

Ping pong readout structure in image sensor with dual pixel supply

An image sensor includes image sensor cells, each configured to generate an image signal in response to control signals. The image sensor also includes an ADC to receive the image signals of the image sensor cells, and a first driver to generate one or more first control signals for a first image sensor cell, where the first driver includes a first negative supply terminal. The image sensor also includes a first multiplexor to selectively connect the first negative supply terminal of the first driver to one of a plurality of power supply nodes, and a second driver to generate one or more second control signals for a second image sensor cell, where the second driver includes a second negative supply terminal. The image sensor also includes a second multiplexor to selectively connect the second negative supply terminal of the second driver to one of the power supply nodes.

Image sensor row driver negative supply connections

Pixel binning for hexa-deca RGBW color filter arrays

Techniques are described for implementing reduced-noise pixel ramp voltage generators for image sensors. The described pixel ramp voltage generators include circuit blocks to address various conventional causes of ramp generator noise. For example, a reference current is generated. Current steering can be used to toggle between a ramp-run mode for generation of a ramp voltage, and a ramp-stop mode for stopping the generation, thereby mitigating changes in low-frequency noise components between pixel conversion cycles, or phases or such cycles. Buffer multiplier techniques can be used to isolate kickback noise of the pixel conversion comparators from components generating the ramp voltage, such as to mitigate image smearing. Some implementations include additional features, such as sample-and-hold techniques used to isolate ramp generation components from current generation component noise, slope calibration techniques to dynamically tune voltage ramp slope, reset techniques, etc.

Pixel ramp generator for image sensor

An image sensor includes a pixel array having a plurality of pixels arranged in rows and columns, a plurality of pixel readout lines coupled to respective pixels, a multiplexing circuit coupled to the pixel readout lines, a plurality of analog-to-digital converters coupled to the multiplexing circuit, and a controller configured to provide pixel readout signals of pixels arranged in a same column to the analog-to-digital converters through the multiplexing circuit for concurrent signal conversion.

Using pixel readout reordering to reduce pattern noise in image sensor

An image sensor includes a controller and a plurality of pixel clusters. Each of the pixel clusters includes a plurality of pixels coupled to a reset transistor, a floating diffusion node, a source follower, and a select transistor. Each pixel of a pixel cluster includes a photodiode, and a transfer transistor having a first terminal coupled to the photodiode, a second terminal coupled to the floating diffusion node, and a gate. The controller is configured to apply a transfer control signal to the gate of the transfer transistor in response to a pixel operation, the transfer control signal being one of a positive voltage level, a negative voltage level, and a ground voltage level.

Two level TX low control for simultaneous improved noise and dark current

A readout circuit includes a ramp generator for generating a plurality of first short ramps having a first level in a reset conversion phase and a plurality of second short ramps having a second level greater than the first level and a full-scale ramp having a third level greater than the second level in a signal conversion phase, a comparator for comparing a first analog signal with each one of the first short ramps to obtain a plurality of first comparison results in the reset conversion phase, and comparing a second analog signal with each one of the second short ramps and the full-scale ramp in the signal conversion phase to generate a plurality of second comparison results and a third comparison result, and a controller configured to determine an output signal value of the second analog signal according to the plurality of second comparison results and the third result.

Fast multi-sampling in image sensors

An image sensor includes a plurality of pixel columns and a plurality of readout circuits. Each readout circuit is coupled to one of the plurality of pixel columns and includes an ADC for receiving a first analog signal of a pixel in a reset conversion phase and a second analog signal of the pixel in a signal measurement phase, a dual-ramp generator for generating a first ramp having a first ramp rate and a second ramp having a second ramp rate greater than the first ramp rate and providing the first ramp to the readout circuits in the reset conversion phase and the second ramp to the plurality of readout circuits in the signal measurement phase, and a controller configured to provide control signals to the readout circuits and the dual-ramp generator.

Dual ramp pixel readout

An apparatus of reading out an image sensor having a plurality of pixels arranged in rows and columns includes a plurality of analog-to-digital converters (ADCs) configured to output digital codes representative of received pixel signals of pixels coupled to respective ADCs, and a smear cancellation circuit configured to determine an average value of the digital codes, multiply the average value by a factor to obtain an offset value, and subtract the offset value from the digital codes to obtain smear-cancelled digital codes.

Reducing smear through digital cancellation in image sensor

Embodiments of clock circuits disclosed herein include a crystal oscillator circuit, an injection oscillator coupled to kick-start the crystal oscillator circuit and a digital frequency calibration circuit coupled to recalibrate the injection oscillator. The crystal oscillator circuit is configured to generate a clock signal at a resonant frequency. The injection oscillator is coupled to supply an oscillation signal at an injection frequency to the crystal oscillator circuit to reduce a start-up time of the crystal oscillator circuit. The digital frequency calibration circuit is coupled to receive the resonant frequency and the injection frequency as inputs, and configured to supply a digital control signal to the injection oscillator to set the injection frequency of the injection oscillator substantially equal to the resonant frequency of the crystal oscillator circuit. Methods are provided herein to recalibrate the injection frequency of an injection oscillator over time, temperature and/or supply voltage.

Growing community of inventors

Austin, TX, United States of America

Matthew Powell