Altera Corporation

Pts Corporation

Cisco Technology, Inc.

Matthew Plonski

Gerald George Pechanek

Ricardo E Rodriguez

David Carl Strube

Kevin Coopman

Ali Soheil Sadri

Navin Jaffer

Anissim A Silivra

Bin Huang

Mark Cameron Cassada

Steven M Lang

Christopher M Olson

Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.

Methods and apparatus for efficient complex long multiplication and covariance matrix implementation

In one embodiment there are provided systems and methods for detecting radio frequency interference (RFI) on a satellite that implements on-board processing. The system leverages an on-board programmable modem complex, and in some cases reprograms portions thereof, to function as an RF spectrum analyzer sensor element that captures and relays received RF information as meta-data to a ground-based system where that information can then be used, on the ground, to generate a spectral display of a received signal at the satellite.

Satellite on-board RFI detection

Techniques for implementing vocoders in parallel digital signal processors are described. A preferred approach is implemented in conjunction with the BOPS&#xae; Manifold Array (ManArray&#x2122;) processing architecture so that in an array of N parallel processing elements, N channels of voice communication are processed in parallel. Techniques for forcing vocoder processing of one data-frame to take the same number of cycles are described. Improved throughput and lower clock rates can be achieved.

Methods and apparatus for efficient vocoder implementations

A digital signal processor for computing various types of complex multiplication is described. The digital signal processor operates in conjunction with registers, a multiplier, an adder, and a multiplexer The Registers store first and second complex operands. The multiplier simultaneously performs multiplications to produce each combination of products between the real and imaginary terms of the first and second complex operands. The multiplexer selects which produced products are added to or subtracted from each other based on the type of complex multiplication being performed. The adder simultaneously performs additions and subtractions, if necessary, to produce both real and imaginary results depending on whether the type of complex multiplication being performed is a conjugated operation. The registers store the results of the complex multiplication.

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Morrisville, NC, United States of America

Matthew Plonski