Advanced Micro Devices Corporation

Matrix Semiconductor, Inc.

Sandisk 3D LLC

Matthew P Crowley

Roy E Scheuerlein

Mark G Johnson

Thomas H Lee

Hamid Partovi

Amos Ben-Meir

Joseph G Nolan, Iii

Luca Giovanni Fasoli

Alper Ilkbahar

Bendik Kleveland

Michael A Vyvoda

Darren R Faulkner

In one embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array and at least two of the following system blocks: an Error Checking & Correction Circuit (ECC); a Checkerboard Memory Array containing sub arrays; a Write Controller; a Charge Pump; a Vread Generator; an Oscillator; a Band Gap Reference Generator; and a Page Register/Fault Memory. In another embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array, ECC, and smart write. The monolithic three-dimensional write-once memory array comprises a first conductor, a first memory cell above the first conductor, a second conductor above the first memory cell, and a second memory cell above the second conductor, wherein the second conductor is the only conductor between the first and second memory cells.

System architecture and method for three-dimensional memory

Two types of topologically different three-dimensional integrated circuits (for example a 4-layer three-dimensional memory array and an 8-layer three-dimensional memory array) are fabricated from a single set of photo-lithographic masks. In one example, masks 1-5 are used along with other masks to create the first four levels of memory cells in both a 4-layer memory array and an 8-layer memory array. The 8-layer memory array is completed with masks used to form the top four layers of the array. An integrated circuit identification circuit generates an appropriate circuit identification signal for both types of integrated circuits by sensing whether a conductive path across some or all of the device levels of the integrated circuit is continuous, and then by selecting the appropriate circuit identification signal.

Method for fabricating and identifying integrated circuits and self-identifying integrated circuits

A tree decoder organization particularly useful for a three-dimensional memory array or any array having very small array line pitch is configured to provide a plurality of top-level decode nodes, each of which, when selected, simultaneously selects a block of array lines and couples each array line of a selected block to a respective intermediate node. Each of the top-level decode signals has a range of control which is substantially less than the extent of the intermediate nodes. In some embodiments each selected block includes more than one array line on each of at least two memory layers having array lines which exit to one side of the memory array. As a result, the large layout area requirement to generate each top-level decode node is supported by a contiguous block of array lines of the memory array.

Tree decoder structure particularly well-suited to interfacing array lines having extremely small layout pitch

A memory array decoder organization readily interfaces to array lines having extremely dense pitch, and in particular interfaces to extremely dense array lines of a three-dimensional memory array. In an exemplary embodiment, a multi-headed decoder includes a group of array line driver circuits associated with a single decode node. Each array line driver circuit couples its associated array line through a first device to an associated upper bias node which is generated to convey either a selected bias condition or an unselected bias condition thereon appropriate for the array line. Each array line driver circuit also couples its associated array line through a second device to an associated lower bias node which is generated to convey an unselected bias condition appropriate for the array line. The array line driver circuits for several different decode nodes may be physically arranged in one or more banks.

Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device

A memory array is subdivided into many sub-arrays which are separately selectable in groups, with each group containing one or more sub-arrays. The various data bits of a data set are physically spread out and mapped into a large number of associated sub-array groups. All the associated sub-array groups are preferably selected during a read cycle to simultaneously read the various bits of the data set, but when writing the data set, a smaller number of sub-array groups are activated during each of several write cycles to simultaneously write only a portion of the data set. Consequently, the read bandwidth remains high and is driven by the number of bits simultaneously read, but the write power is reduced since during each write cycle fewer bits are written. Such a memory array is particularly advantageous with passive element memory cells, such as those having antifuses.

Partial selection of passive element memory cell sub-arrays for write operation

Two types of topologically different three-dimensional integrated circuits (for example a 4-layer three-dimensional memory array and an 8-layer three-dimensional memory array) are fabricated from a single set of photolithographic masks. In one example, masks 1-5 are used along with other masks to create the first four levels of memory cells in both a 4-layer memory array and an 8-layer memory array. The 8-layer memory array is completed with masks used to form the top four layers of the array. An integrated circuit identification circuit generates an appropriate circuit identification signal for both types of integrated circuits by sensing whether a conductive path across some or all of the device levels of the integrated circuit is continuous, and then by selecting the appropriate circuit identification signal.

Partial selection of passive element memory cell sub-arrays for write operations

A charge pump circuit includes, in a preferred embodiment, a plurality of serially-connected pump stages, each of which is driven by one or more associated clock signals for the stage. The amplitude of the clock signals associated with a respective one of the pump stages differ in amplitude from that of the clock signals associated with at least one other pump stage. As a result, the additional voltage achieved by each successive pump stage may be progressively larger for each successive pump stage. An exemplary charge pump circuit provides clock signals which increase in amplitude with each successive pump stage, and provides with each successive pump stage an output voltage having a magnitude that is a multiplicative factor of the magnitude of the input voltage for the stage. Consequently, the output voltage achieved by the exemplary charge pump circuit is an exponential function of the number of pump stages within the charge pump circuit.

Charge pump circuit

A passive element memory array preferably biases selected X-lines to an externally received V voltage and selected Y-lines to ground. Unselected Y-lines are preferably biased to V minus a first offset voltage, and unselected X-lines biased to a second offset voltage (relative to ground). The first and second offset voltages preferably are identical and have a value of about 0.5 to 2 volts. The V voltage depends upon the memory cell technology used, and preferably falls within the range of 5 to 20 volts. The area otherwise required for an on-chip V generator and saves the power that would be consumed by such a generator. In addition, the operating temperature of the integrated circuit during the programming operation decreases, which further decreases power dissipation. When discharging the memory array, the capacitance between layers is preferably discharged first, then the layers are discharged to ground.

Method and apparatus for discharging memory array lines

In a data processing system, a circuit for providing an even bus clock signal, EVENB,, when the leading edges of the bus clock signal B,and a processor clock signal P,are coincident includes a phase-locked loop unit and a coincidence unit. The phase-locked loop unit provides P,signals that have a frequency Nx the frequency of the B,signals, where N can have an integer or a half integer value. The phase-locked loop unit includes a divide-by-M unit, where M&equals;2N, that receives the P,signal at an input terminal and applies an output signal, P,/M, to the phase detector unit of the phase-locked loop unit. The operation of the phase-locked loop results in the B,signal and the P,/M signal having an established phase relationship. The P,signal and the P,/M signal are applied to the coincidence unit, the simultaneous application of the two signals resulting in the coincidence unit providing the EVENB,signals. When N is an integer, the P,signal and the B,signal have coincident rising edges that do not coincide with a leading edge of a P,/M signal. In this situation, a delayed signal, triggered by a previous P,/M signal, is generated that is applied to the coincidence unit in place of the missing P,/M signal to provide the EVENB,signal.

Apparatus and method for a coincident rising edge detection circuit

A power supply filter capable of functioning with low power supply voltages includes a resistor-capacitor circuit coupled to a power supply line and a transistor for providing power to a target circuit, such as a phase-locked loop circuit, coupled between the resistor-capacitor circuit and the power supply line. The resistor-capacitor circuit is coupled to a charge pump controller to keep the transistor in a saturation state. The charge pump controller receives at least one clock signal that is coupled to at least one capacitive circuit. The at least one capacitive circuit includes at least two capacitors in series with a biased middle node located between the at least two capacitors in order to provide immunity to time dependent dielectric breakdown, the middle node coupled to approximately half the power supply line. A method of filtering noise from a power supply includes providing an N-channel source follower circuit coupled between the power supply and a target circuit, the N-channel source follower circuit including a resistor-capacitor circuit and a transistor with a threshold voltage. The method also includes maintaining the transistor in a saturation state through placing a charge pump in the N-channel source follower circuit, the charge pump receiving a first clock signal and a second clock signal, and allowing the voltage provided to a target circuit to exceed the voltage of the power line minus the threshold voltage while maintaining the transistor in a saturation state.

PLL power supply filter (with pump) having a wide voltage range and immunity to oxide overstress

An electronic system such as a processor or computer system includes a phase-locked loop (PLL) having a PLL parameter modification circuit. In one embodiment, the PLL parameter modification circuit may be programmed to provide one of several current control signals to a charge pump. Additionally, the PLL parameter modification circuit may be programmed to alter a loop filter transfer function by selectively changing resistance and/or capacitance values of the loop filter. Each current control signal modifies the charge pump output control voltage to a VCO differently, and, thus, modifying the current control signals to the charge pump effectively modifies the bandwidth of the PLL. In one embodiment, the PLL parameter modification circuit modifies current control signals to the charge pump by selectively inserting and removing, in accordance with programmable register bit(s) states, diode configured transistors in a current mirror configuration. Thus, a ratio of the output current of the current mirror i.e. the current control signals, to a current reference signal may be programmably modified to modify the bandwidth and lock time parameters of the PLL. The PLL parameter modification may modify the resistive and capacitive parameters of the loop filter by selecting configuring multiple resistors and capacitors to form one of many equivalent circuits.

Phase-locked loop with variable parameters

A differential signal generator for generating a true/complement output signal pair in response to a single-ended input signal is disclosed. The differential signal generator includes an input stage that generates a true/complement intermediate signal pair in response to the input signal, and first and second inverters that generate the output signal pair in response to the intermediate signal pair. The first and second inverters have dynamic beta ratios that change in response to the input signal. This is accomplished by coupling a transistor in the first inverter to ground and decoupling a transistor in the second inverter from ground when the input signal has a high value, and decoupling the transistor in the first inverter from ground and coupling the transistor in the second inverter to ground when the input signal has a low value. As a result, the output signal pair cross each other at a predetermined cross-point although the intermediate signal pair does not.

Differential signal generator with dynamic beta ratios

An electronic system such as a processor or computer system includes circuitry that supports a plurality of clock modes. The clock modes may be used for, for example, testing for critical paths. The clock modes include a variety of clock signal variations that may be utilized such as cycle stretch clock mode, pulse or delay fault mode, and stop mode which provide substantial flexibility in support of a multitude of tests. In one embodiment, a processor of an electronic system includes test clock mode circuitry to support and utilize test clock modes without dependence on an external bypass clock signal operating at processor operational frequencies. Furthermore, the processor implements the test clock modes at full processor operational frequencies. Additionally, a phase-locked loop is utilized to synchronize test mode clock signals with a reference clock signal to, for example, facilitate realistic operational conditions and acquisition of accurate test results. Additionally, in some test clock modes, the phase-locked loop may be synchronized prior to issuing test clock signals to, for example, further support realistic processor operational conditions during, for example, testing operations.

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San Jose, CA, United States of America

Matthew P Crowley