Apple Inc.

Microsoft Technology Licensing, LLC

Matthew N Papakipos

Jerome Francis Duluk, Jr

Joseph P Bratt

Richard E Hessel

Stephen L Dodgen

Nathan D Tuck

Jason Rupert Redgrave

Emerson S Fang

Sushma Shrikant Trivedi

Vaughn Todd Arnold

Jack Benkual

Sidong Li

Hengwei Hsu

Sam Ng

George Cuan

Zhaoyu Gong

Thomas Y Ho

Tuan Anh Nguyen

Abbas Rashid

Shun Wai Go

Abraham Mammen

Bo Hong

Joseph P Grass

Lindy Fung

Albert Suan-Wei Tsay

Henry Packard Moreton

Carroll Philip Gossett

Christian Pappas

Robert J Williamson

Thomas Y Yo

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Deferred shading graphics pipeline processor having advanced features

The present invention comprises a computer implemented process and system for rendering curves or surfaces as 3D graphics on a display. The system of the present invention includes a computer system having a processor, a bus, and a 3D graphics rendering pipeline. The curves or surfaces are modeled by non-uniform rational B-splines (NURBS). The process of the present invention functions by receiving a NURBS model for rendering from a software program running on the host processor. The NURBS model defines a curve or surface. The process of the present invention efficiently converts the NURBS model to a Bezier model using the hardware of the graphics rendering pipeline. The Bezier model describes the same curve or surface. The process of Bezier model and the graphics rendering pipeline. The points are then used by the graphics rendering pipeline to render the curve or surface defined by the Bezier model. Alternatively, a NURBS model is directly evaluated into a plurality of points on a curve or surface, and in turn, rendered into the curve or surface. This direct rendering of the NURBS model is implemented using the graphics rendering pipeline.

Method and system for efficiently evaluating and drawing NURBS surfaces for 3D graphics

The present invention comprises a computer implemented process and system for rendering curves or surfaces as 3D graphics on a display. The system of the present invention includes a computer system having a processor, a bus, and a 3D graphics rendering pipeline. The curves or surfaces are modeled by non-uniform rational B-splines (NURBS). The process of the present invention functions by receiving a NURBS model for rendering from a software program running on the host processor. The NURBS model defines a curve or surface. The process of the present invention efficiently converts the NURBS model to a Bezier model using the hardware of the graphics rendering pipeline. The Bezier model describes the same curve or surface. The process of the present invention subsequently generates a plurality of points on the curve or surface using the Bezier model and the graphics rendering pipeline. The points are then used by the graphics rendering pipeline to render the curve or surface defined by the Bezier model. Alternatively, a NURBS model is directly evaluated into a plurality of points on a curve or surface, and in turn, rendered into the curve or surface. This direct rendering of the NURBS model is implemented using the graphics rendering pipeline.

A system and method for performing tangent space lighting in a deferred shading graphics processor (DSGP) encompasses blocks of the DSGP that preprocess data and a Phong shader that executes only after all fragments have been preprocessed. A preprocessor block receives texture maps specified in a variety of formats and converts those texture maps to a common format for use by the Phong shader. The preprocessor blocks provide the Phong shader with interpolated surface basis vectors (v , v , n), a vector Tb that represents in tangen/object space the texture/bump data from the texture maps, light data, material data, eye coordinates and other information used by the Phong shader to perform the lighting and bump mapping computations. The data from the preprocessor is provided for each fragment for which lighting effects need to be computed. The Phong shader computes the color of a fragment using the information provided by the preprocessor. The Phong shader performs all lighting computations in eye space, which requires it first to transform bump data from tangent space to eye space. In one embodiment the Phong hardware does this by multiplying a matrix M whose columns comprise eye space basis vectors (b , b , n) derived from the surface basis vectors (v , v , n) and the vector Tb of bump map data. The eye space basis vectors are derived by the DSGP preprocessor so that the multiplication (M&times;Tb) gives the perturbed surface normal N&prime; in eye space, reflecting the bump effects. The perturbed surface normal N&prime; is subsequently used in the lighting computations.

Method and apparatus for performing tangent space lighting and bump mapping in a deferred shading graphics processor

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and multiple-stage hidden surface removal processing, as well as other structures and/or procedures. Embodiments of the present invention are designed to provide high-performance 3D graphics with Phong shading, subpixel anti-aliasing, and texture- and bump-mappings.

Graphics processor with deferred shading

Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is a Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch & decode (,), a geometry unit (,), a mode extraction (,) and polygon memory (,), a sort unit (,) and sort memory (,), a setup unit (,), a cull unit (,), a mode injection (,), a fragment unit (,), a texture (,) and texture memory (,) a phong shading (,), a pixel unit (,), a backend unit (,) coupled to a frame buffer (,). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.

Deferred shading graphics pipeline processor

Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch decode (,), a geometry unit (,), a mode extraction (,) and polygon memory (,), a sort unit (,) and sort memory (,), a setup unit (,), a cull unit (,), a mode injection (,), a fragment unit (,), a texture (,) and texture memory (,) a phong shading (,), a pixel unit (,), a backend unit (,) coupled to a frame buffer (,). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.

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Menlo Park, CA, United States of America

Matthew N Papakipos