Agere Systems Inc.

Matthew Moucheron

John Michael Sharpe

Mary Drummond Roby

John Anthony Pantone

Carl A Benevit

Jerome Chu

Shane S Dias

The present invention provides a non-global process for designing an integrated circuit layout. The process comprises locating an isolated layout feature of an integrated circuit layout and non-globally changing at least one lateral dimension of the isolated layout feature to obtain an optimized increment. The change in lateral dimension by the optimized increment does not violate a minimum separation distance between the isolated layout feature and the other adjacent layout features. The process may be incorporated into a system for non-globally modifying an integrated circuit layout, described in a data file or an integrated circuit design system.

Process for the selective control of feature size in lithographic processing

A process for evaluating and correcting virtual integrated circuit designs includes a method and apparatus for determining a ratio of an amount of material, i.e. polysilicon or metal, in any given layer to an area of the layer. The ratio is then compared to a predetermined target ratio, which is based on a ratio of the total amount of the material to the entire area of the I-C design. The process then automatically inserts or deletes an amount of material from the layer as needed, using any of four methods. These methods include deletion, scaling, deletion and scaling or striping. The ratio for an erroneous layer is rechecked after the first correction is performed and the entire process is repeated using a Newton-Raphson or a Least Absolute Deviation Regression method until the ratio falls within the predetermined tolerances. If the layer has been filled, the layer is further checked for short circuits, fill isolation violations, antenna violations and the like which may have resulted from the material fill. The evaluation and correction process proceeds for each layer of the virtual integrated circuit design until the entire design has been evaluated and corrected.

Method and apparatus for evaluating and correcting errors in integrated circuit chip designs

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Allentown, PA, United States of America

Matthew Moucheron