University of South Florida

Matthew Morrison

Nagarajan Ranganathan

Jarred Adam Ligatti

An adiabatic dynamic differential logic circuit is provided for mitigating a differential power analysis (DPA) attack on a secure integrated chip including a plurality of transistors configured to perform each of a plurality of two-input logical output calculations, wherein each of the two-input logical output calculations results in a minimal differential power of the logic circuit. In one embodiment, a high-performance adiabatic dynamic differential logic circuit is provided which is optimized for very high operating frequencies. In another embodiment, a body-biased adiabatic dynamic differential logic circuit is provided which utilizes transistor body biasing to improve the switching time and differential power of the design.

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Oxford, MS, United States of America

Matthew Morrison