International Business Machines Corporation

Matthew Michael Viens

Larry LeeRoy Tretter

Melanie Jean Sandberg

An apparatus according to one embodiment includes a hardware based controller that is configured to perform operations. The operations include performing anti-aliasing filtering on each of a plurality of signals, each signal having a frequency that is a different fraction of a frequency of a data read clock. An amplitude is measured of each of the signals after the anti-aliasing filtering. Moreover, the operations include determining whether the measured amplitudes of the signals are within a predefined range. Anti-aliasing settings used during the anti-aliasing filtering are stored in response to a determination that the amplitudes of the signals are within the predefined range. The anti-aliasing settings are changed in response to a determination that the amplitudes of the signals are outside the predefined range.

In-circuit calibration of anti-aliasing filter

A computer-implemented method according to one embodiment includes performing anti-aliasing filtering on each of a plurality of signals, each signal having a frequency that is a different fraction of a frequency of a data read clock. An amplitude of each of the signals is measured after the anti-aliasing filtering. In response to the amplitudes of the signals being within a predefined range, anti-aliasing settings used during the anti-aliasing filtering are stored. In response to the amplitudes of the signals being outside the predefined range, the anti-aliasing settings are changed. A computer program product according to another embodiment includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. The program instructions are executable by a processing circuit to cause the processing circuit to perform the foregoing method.

A computer-implemented method, according to one embodiment, includes, performing anti-aliasing filtering on each of a plurality of symmetrical square wave signals, each symmetrical square wave signal having a frequency that is a different fraction of a frequency of a data read clock. The filtered symmetrical square wave signals are passed through a band pass filter. An amplitude of each of the symmetrical square wave signals is measured after the band pass filtering. In response to the amplitudes of the symmetrical square wave signals being within a predefined range, anti-aliasing settings used during the anti-aliasing filtering are stored. In response to the amplitudes of the symmetrical square wave signals being outside the predefined range, the anti-aliasing settings are changed.

A computer-implemented method, according to one embodiment, includes, for a particular data read clock value, generating a series of symmetrical square wave signals, each having a frequency that is a different fraction of the data read clock frequency. Anti-aliasing filtering is performed on each of the symmetrical square wave signals using predefined anti-aliasing settings. The filtered symmetrical square wave signals are passed through a band pass filter, the band pass filter being set to pass a single harmonic frequency of each of the symmetrical square wave signals. An amplitude of each of the band pass filtered symmetrical square wave signals is measured. In response to the amplitudes of the symmetrical square wave signals being within a predefined range, the anti-aliasing settings are stored. In response to the amplitudes of the symmetrical square wave signals being outside the predefined range, the anti-aliasing settings are changed, and the method is repeated.

In-circuit calibration method of anti-aliasing filter

A method for low density parity code decoding according to one embodiment includes sequentially processing groups of variable node (vnode) values associated with a codeword using a plurality of vnode logic modules and outputting updated vnode values; storing the vnode values and updated vnode values in a vnode memory; sequentially processing groups of cnode values using a plurality of check node (cnode) logic modules and outputting updated vnode values; storing the (mode values and updated (mode values in a mode memory; and checking the codeword using the updated vnode values and the updated mode values.

Systems and methods for efficient low density parity check (LDPC) decoding

A system for low density parity code decoding according to one embodiment includes a plurality of variable node (vnode) logic modules for sequentially processing groups of vnode values associated with a codeword and outputting updated vnode values; a vnode memory for storing the vnode values and updated vnode values; a plurality of check node (cnode) logic modules for sequentially processing groups of cnode values and outputting updated vnode values; a cnode memory for storing the cnode values and updated cnode values; and logic for checking the codeword using the updated vnode values and the updated cnode values. Additional systems and methods are also presented.

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Tucson, AZ, United States of America

Matthew Michael Viens