Qualcomm Incorporated

Unisys Corporation

Qualcomm Mems Technologies, Inc.

Other

Philips Healthcare Informatics, Inc.

Matthew Michael Nowak

Jonghae Kim

Shiqun Gu

Seung Hyuk Kang

Changhan Hobie Yun

Mario Francisco Velez

Xia Li

Daeik Daniel Kim

Chengjie Zuo

Je-Hsiung Lan

Xiaochun Zhu

David Francis Berdy

Robert Paul Mikulka

Brian Matthew Henderson

Kenneth Kaskoun

Kangho Lee

Lew G Chua-Eoan

Thomas R Toms

Feng Wang

Jeffrey Xu

Steven Mark Millendorf

Stanley Seungchul Song

Choh Fei Yeap

Xiangdong Zhang

David Merrill Jacobson

Xu Guo

Nicholas K Yu

Francesco Carobolante

Hari Rao

Vladimir Machkaoutsan

Mustafa Badaroglu

Chi Shun Lo

Puay Hoe See

Jung Pill Kim

Junjing Bao

Jungwon Suh

Jeffrey Alexander Levin

John Jianhong Zhu

Robert P Gilmore

Niranjan Sunil Mudakatte

Seyfollah Seyfollahi Bazarjani

Ranadeep Dutta

Sang-June Park

Wenqing Wu

Wah Nam Hsu

Asaf Ashkenazi

Tae Hyun Kim

Rongtian Zhang

Wuyang Hao

Yu Cao

Wei Zhao

Lawrence D Smith

Clarence Chui

Kern Rim

Evgeni Petrovich Gousev

Edgar Schmidhammer

Zhongze Wang

Ravindra Vaman Shenoy

Richard Hammond

Christian Hoffmann

Wei-Chuan Chen

Russel A Martin

Milind Shah

Taehyun Kim

Anand Srinivasan

Gengming Tao

Dong Wook Kim

Sungryul Kim

Philip Jason Stephanou

Yu Lu

Xiaonan Chen

Reza Jalilizeinali

Eugene Dantsker

Da Yang

Daniel Daeik Kim

Xiao Lu

Kendrick Hoy Leong Yuen

Barry Matsumori

Kendrick H Yuen

Michael Laisne

Stefan Leopold Hatzl

Xiaoju Yu

David Bang

Roland D Rothenberger

Manuel Hofer

Mark A Vinson

Nicholas Ka Ming Yu

Manoj Bhatnagar

Roawen Chen

Hongjun Yao

Glen T Kim

Mark C Chan

Jeong Hwan Yang

Ronnie A Lindley

Jiayu Xu

Sean Li

Ken Lee

Rodrigo Pacher Fernandes

Robert J Walden

Peter Bainschab

An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

Integrated circuits (ICs) on a glass substrate

A passive on glass (POG) on filter capping apparatus may include an acoustic filter die. The apparatus may further include a capping die electrically coupled to the acoustic filter die. The capping die may include a 3D inductor.

Integration of through glass via (TGV) filter and acoustic filter

A semiconductor device comprises a complementary metal oxide semiconductor (CMOS) device and a heterojunction bipolar transistor (HBT) integrated on a single die. The CMOS device may comprise silicon. The HBT may comprise III-V materials. The semiconductor device may be employed in a radio frequency front end (RFFE) module to reduce size and parasitics of the RFFE module and to provide cost and cycle time savings.

Integrated semiconductor devices and method of fabricating the same

Examples of monolithic integrated emitter-detector array in a flexible substrate for biometric sensing and associated devices and methods are disclosed. One disclosed example device includes a flexible substrate; a first array of emitters embedded in the flexible substrate, the first array of emitters configured to emit first electromagnetic (EM) signals; a first array of detectors embedded in the flexible substrate, the first array of detectors configured to detect reflections of the first EM signals; a first scanning circuit coupled to the first array of emitters, the first scanning circuit configured to selectively activate individual emitters of the first array of emitters; and a first sensing circuit coupled to individual detectors of the first array of detectors, the first sensing circuit configured to receive a detection signal from at least one of the detectors of the first array of detectors.

Monolithic integrated emitter-detector array in a flexible substrate for biometric sensing

Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a multichip module or device, such as a multichip module or device with flip-chip (FC) bumps. Intra-module shielding between individual chips within the multichip module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a substrate or interposer to ensure reliable grounding.

Compartment shielding in flip-chip (FC) module

A tunable capacitor may include a first terminal having a first semiconductor component with a first polarity. The tunable capacitor may also include a second terminal having a second semiconductor component with a second polarity. The second component may be adjacent to the first semiconductor component. The tunable capacitor may further include a first conductive material electrically coupled to a first depletion region at a first sidewall of the first semiconductor component.

CMOS and bipolar device integration including a tunable capacitor

A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.

Nanowire device with reduced parasitics

A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.

Vertically stacked nanowire field effect transistors

A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.

Two-stage power delivery architecture

An apparatus is disclosed that includes a frequency multiplexer circuit coupled to an input node and configured to receive an input signal via the input node. The frequency multiplexer circuit comprises a first filter circuit, a second filter circuit, and a third filter circuit. The apparatus also includes a switching circuit that is configurable to couple at least two of a first output of the first filter circuit, a second output of the second filter circuit, or a third output of the third filter circuit to a single output port.

Frequency multiplexer

Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) and related components and methods

Self-aligned metal cut and via for Back-End-Of-Line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices, is disclosed. In this manner, mask placement overlay requirements can be relaxed. This relaxation can be multiples of that allowed by conventional BEOL techniques. This is enabled through application of different fill materials for alternating lines in which a conductor will later be placed. With these different fill materials in place, a print cut and via mask is used, with the mask allowed to overlap other adjacent fill lines to that of the desired line. Etching is then applied that is selective to the desired line but not adjacent lines.

Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices

An integrated circuit (IC) includes a first semiconductor device on a glass substrate. The first semiconductor device includes a first semiconductive region of a bulk silicon wafer. The IC includes a second semiconductor device on the glass substrate. The second semiconductor device includes a second semiconductive region of the bulk silicon wafer. The IC includes a through substrate trench between the first semiconductive region and the second semiconductive region. The through substrate trench includes a portion disposed beyond a surface of the bulk silicon wafer.

Integrated circuits (ICS) on a glass substrate

Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits are disclosed. In some aspects, an RF circuit includes CMOS devices, a silicon substrate having doped regions that define the CMOS devices, and a trench through the silicon substrate. The trench through the silicon substrate forms a continuous channel around the doped regions of one of the CMOS devices to electrically isolate the CMOS device from other CMOS devices embodied on the silicon substrate. By so doing, performance characteristics of the CMOS device, such as linearity and signal isolation, may be improved over those of conventional CMOS devices (e.g., bulk CMOS).

Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits

Growing community of inventors

San Diego, CA, United States of America

Matthew Michael Nowak