Microchip Technology Inc.

Matthew Martin

Sonu Daryanani

Bomy A Chen

Gilles Festes

A memory cell having a structure of a modified flash memory cell, but configured to operate in a low voltage domain (e.g., using voltages of &#x2264;6V amplitude for program and/or erase operations) is provided. The disclosed memory cells may be formed with dielectric layers having reduced thickness(es) as compared with conventional flash memory cells, which allows for such low voltage operation. The disclosed memory cells may be compatible with advanced, high density, low energy data computational applications. The disclosed memory cells may replace or reduce the need for RAM (e.g., SRAM or DRAM) in a conventional device, e.g., microcontroller or computer, and are thus referred to 'RAM Flash' memory cells. Data retention of RAM Flash memory cells may be increased (e.g., to days, months, or years) by (a) applying a static holding voltage at selected nodes of the cell, and/or (b) periodically refreshing data stored in RAM Flash.

Flash memory cell adapted for low voltage and/or non-volatile performance

Embodiments of the present disclosure provide systems and methods for improving the read window in a split-gate flash memory cell, e.g., by biasing the control gate terminal with a non-zero (positive or negative) voltage during cell read operations to improve or control the erased state read performance or the programmed state read performance of the cell. A method of operating a split-gate flash memory cell may include performing program operations, performing erase operations, and performing read operations in the cell, wherein each read operation includes applying a first non-zero voltage to the word line, applying a second non-zero voltage to the bit line, and applying a third non-zero voltage Vto the control gate.

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Gilbert, AZ, United States of America

Matthew Martin