International Business Machines Corporation

Matthew Mantell Ziegler

Hung-Yi Liu

Ruchir Puri

Minsik Cho

Haoxing Ren

Hua Xiang

Lakshmi Narasimha Reddy

George Diedrich Gristede

Rajiv V Joshi

Chin Ngai Sze

Sourav Saha

Christopher J Berry

Robert Louis Franch

Dorothy Kucar

Michael H Wood

Haifeng Qian

Alvan Wing Ng

Louise Helen Trevillyan

Xiaoping Tang

Jagannathan Narasimhan

Michael D Amundson

Victor N Kravets

Smita Krishnaswamy

John Thomas Badar

David W Lewis

Embodiments for tuning parameters to a synthesis program are provided. At least one set of parameter settings for the synthesis program is selected. A plurality of identical synthesis jobs for the at least one set of parameter settings is run in an iteration of the synthesis program. Results of the iteration of the synthesis program are analyzed utilizing a tuning optimization cost function. Combinations of the parameter settings are created based on the analysis. At least one synthesis job for is run each of the combinations of the parameter settings in a subsequent iteration of the synthesis program. The analysis of the results, the creating of the combinations of parameter settings, and the running at the at least one synthesis job for each of the combinations of parameter settings are repeated until an exit criteria has been achieved.

Methods and systems for leveraging computer-aided design variability in synthesis tuning

A computer-implemented method obtains data describing a plurality of synthesis scenarios associated with a very-large-scale integration design (VLSI), wherein each synthesis scenario describes a different combination of tunable design parameters for a macro of the VLSI design, and wherein the VLSI design includes a plurality of macros being tuned. The plurality of macros is ranked based on the data. The ranking produces a macro waiting list that identifies those of the synthesis scenarios that are associated with each of the macros. A subset of the synthesis scenarios is pushed from the macro waiting list to a job submission queue that is separate from the macro waiting list. The job submission queue ranks the subset of synthesis scenarios in an order in which they are to be synthesized by a synthesis tuning system. At least one synthesis scenario is submitted to the synthesis tuning system according to the order.

Scheduling simultaneous optimization of multiple very-large-scale-integration designs

Disclosed is a system, computer program product, and method for performing logic, physical synthesis, and post-route optimization. The method begins with identifying a plurality of groups of paths in a circuit by a unique criteria. The unique criteria is any one of a netlist regular expression, a cell topology regular expression, a physical structure, or a combination thereof. An optimization process is performed on the design and is repeated until the cumulative histogram corresponds to the reference histogram within a threshold. The histogram optimization on the group of paths to make the cumulative histogram correspond to the reference cumulative histogram can be adjusted to account for timing, power, yield, or a combination thereof. After a first group of paths has been optimized, the process can be repeated for other groups of paths. The histogram optimization performed on each group of paths is merged into overall histogram optimization design.

Optimizing the layout of circuits based on multiple design constraints

A booster for a digital circuit block provides speed and reliability at lower static power supply voltages, reducing overall power consumption of the circuits. The booster includes a transistor that couples a dynamic power supply node to a static power supply and is disabled in response to a boost clock. An inductor and capacitance, which may be the block power supply shunt capacitance, coupled to the dynamic power supply resonates so that the voltage of the dynamic power supply increases in magnitude to a value greater the static power supply voltage. A boost transistor is included in some embodiments to couple an edge of the clock to the dynamic power supply, increasing the voltage rise. Another aspect of the booster includes multiple boost transistors controlled by different boost clock phases so that the resonant boost circuit is successively stimulated to increase the amount of voltage rise.

Resonant virtual supply booster for synchronous digital circuits having a predictable evaluate time

A method and system are provided for tuning parameters of a synthesis program for a design description. The method includes (a) ranking individual parameter impact by evaluating a design-cost function of each of the parameters. The method further includes (b) creating a set of possible parameter combinations that is ordered by an estimated-cost function. The method additionally includes (c) selecting, from the set of possible parameter combinations, top-k scenarios having best estimated costs to form a potential set, and running at least some of the top-k scenarios in parallel through the synthesis program. The method also includes (d) repeating steps (b)-(c) for one or more iterations until at least one of a maximum iteration limit is reached and an exit criterion is satisfied.

Enhanced parameter tuning for very-large-scale integration synthesis

In one aspect, a method for tuning input parameters to a synthesis program is provided which includes the steps of: (a) selecting a subset of parameter settings for the synthesis program based on a tuning optimization cost function; (b) individually running synthesis jobs in parallel for each of the parameter settings in the subset; (c) analyzing results from a current iteration and prior iterations, if any, using the cost function; (d) using the results from the current iteration and the prior iterations, if any, to create combinations of the parameter settings; (e) running synthesis jobs in parallel for the combinations of the parameter settings in a next iteration; and (f) repeating the steps (c)-(e) for one or more additional iterations or until an exit criteria has been met.

Synthesis tuning system for VLSI design optimization

A system and method of performing an intra-run decision during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design are described. The method includes executing a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters, and determining a quality measure associated with each of the two or more scenarios. The method also includes performing the intra-run decision by eliminating one or more of the two or more scenarios for execution in a subsequent stage of the synthesis based on the quality measure associated with each of the two or more scenarios.

Intra-run design decision process for circuit synthesis

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Matthew Mantell Ziegler