Advanced Micro Devices Corporation

Matthew M Crum

Matthew Andrew Rafacz

Gregory William Smaus

Emil Talpes

Michael David Achenbach

Francesco Spadini

Christopher J Burke

Michael T Clark

John M King

David N Suggs

Teik-Chung Tan

Michael E Tuuk

Mahesh Subramony

Roof rack crossbar assembly for a convertible sport utility vehicle

Techniques for selectively executing a lock instruction speculatively or non-speculatively based on lock address prediction and/or temporal lock prediction. including methods an devices for locking an entry in a memory device. In some techniques, a lock instruction executed by a thread for a particular memory entry of a memory device is detected. Whether contention occurred for the particular memory entry during an earlier speculative lock is detected on a condition that the lock instruction comprises a speculative lock instruction. The lock is executed non-speculatively if contention occurred for the particular memory entry during an earlier speculative lock. The lock is executed speculatively if contention did not occur for the particular memory entry during an earlier speculative lock.

Lock address contention predictor

An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located.

Store-to-load forwarding

A method of operating a processing unit includes, in response to detecting that the processing unit is operating in a voltage limited state, calculating a set of headroom values by calculating a headroom value for each operational constraint in a set of operational constraints of the processing unit, based on the calculated set of headroom values, selecting from a set of performance features a subset of one or more performance features for enabling in the processing unit, and enabling the selected subset of performance features in the processing unit.

Enabling performance features for voltage limited processors

For a memory access at a processor, only a subset (less than all) of the ways of a cache associated with a memory address is prepared for access. The subset of ways is selected based on stored information indicating, for each memory access, which corresponding way of the cache was accessed. The subset of ways is selected and preparation of the subset of ways is initiated prior to the final determination as to which individual cache way in the subset is to be accessed.

Way preparation for accessing a cache

A processor includes a store queue that stores information representing store instructions. In response to retirement of a store instruction, the processor invalidates the corresponding entry in the store queue, thereby indicating that the entry is available to store a subsequent store instruction. The store address is not removed from the queue until the subsequent store instruction is stored. Accordingly, the store address is available for comparison to a dependent load address.

Confirming store-to-load forwards

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Austin, TX, United States of America

Matthew M Crum