Intel Corporation

Matthew M Bace

Ian M Steiner

Krishnakanth Venkata Sistla

Ankush Varma

Avinash N Ananthakrishnan

Martin Rowland

Efraim Rotem

Eliezer Weissmann

Jason W Brandt

Stephen H Gunther

Alon Naveh

Jeremy J Shrall

Vivek Garg

Anil Aggarwal

Chris Poirier

Eric J DeHaemer

Daniel G Borkowski

James Ignowski

Mark Rowland

Eric Dehaemer

Vinodh Gopal

William C Hasenplaugh

Malini Krishnan Bhandaru

Scott P Bobholz

Gunnar Gaubatz

Jeffrey S Wilder

A Leonard Brown

Chelsea Akturan

Cagdas Akturan

In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

User level control of power management policies

In an embodiment, a processor comprises: a plurality of cores each to execute instructions; a plurality of thermal sensors, at least one of which is associated with each of the cores; and a power control unit (PCU) coupled to the cores. The PCU includes a thermal control logic to preemptively throttle a first core by a first throttle amount when a temperature of a second core exceeds at least one thermal threshold. Note that this first core may be preemptively throttled independently of a throttling of the second core and may have a temperature of the first core does not exceed any thermal threshold. Other embodiments are described and claimed.

Adaptive algorithm for thermal throttling of multi-core processors with non-homogeneous performance states

An apparatus and method for managing a frequency of a computer processor. The apparatus includes a power control unit (PCU) to manage power in a computer processor. The PCU includes a data collection module to obtain transaction rate data from a plurality of communication ports in the computer processor and a frequency control logic module coupled to the data collection module, the frequency control logic to calculate a minimum processor interconnect frequency for the plurality of communication ports to handle traffic without significant added latency and to override the processor interconnect frequency to meet the calculated minimum processor interconnect frequency.

Method and apparatus for setting an I/O bandwidth-based processor frequency floor

In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.

Dynamically modifying a power/performance tradeoff based on a processor utilization

In an embodiment, a processor includes a plurality of cores each to independently execute instructions, and a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a control logic to reduce a maximum operating frequency of the processor if a first number of forced performance state transitions occurs in a first time period or a second number of forced performance state transitions occurs in a second time period. Other embodiments are described and claimed.

Adaptively limiting a maximum operating frequency in a multicore processor

Dynamically modifying a power/performance tradeoff based on processor utilization

A processor is described that includes a processing core and a plurality of counters for the processing core. The plurality of counters are to count a first value and a second value for each of multiple threads supported by the processing core. The first value reflects a number of cycles at which a non sleep state has been requested for the first value's corresponding thread, and, a second value that reflects a number of cycles at which a non sleep state and a highest performance state has been requested for the second value's corresponding thread. The first value's corresponding thread and the second value's corresponding thread being a same thread.

Processor having per core and package level P0 determination functionality

Techniques are described to multiply two numbers, A and B. In general, multiplication is performed by using Karatsuba multiplication on the segments of A and B and adjusting the Karatsuba multiplication based on the values of the most significant bits of A and B.

Multiplying two numbers

According to some embodiments, cipher block chaining decryption is performed.

Cipher block chaining decryption

A method of processing data includes writing a data block of size m where m is greater than zero into a queue. The method also includes reading a data block of size n where n is greater than zero from the queue and where the size of n is different from the size of m. The queue can be a FIFO queue. The queue can also have a configurable size.

Writing and reading data from a queue

A method and apparatus for providing the header checksum of a data packet.

Providing a header checksum for packet data communications

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Andover, MA, United States of America

Matthew M Bace