Arm Limited

Matthew Lucien Evans

Jason Parker

Gareth Rhys Stockwell

Richard Roy Grisenthwaite

Martin Weidmann

Djordje Kovacevic

Andrew Christopher Rose

Bruce James Mathewson

David Hennah Mansell

Nigel John Stephens

Andrew Brookfield Swaine

Adam James McNeeney

Anthony Jebson

Robert Gwilym Dimond

Gareth James Evans

Ali Ghassan Saidi

Paul Gilbert Meyer

Frederic Claude Marie Piry

Phanindra Kumar Mannava

Albin Pierrick Tonnerre

Andrew John Turner

Christopher Vincent Severino

Seow Chuan Lim

Hakan Lars-Goran Persson

Jelena Milanovic

Håkan Lars-Göran Persson

Geoffrey Wyman Blake

Carlos Garcia-Tobin

Håkan Persson

Anirruddha Nagendran Udipi

Stanislaw Czerniawski

Aris Doros Aristodemou

An apparatus and method are provided for storing a plurality of translation entries in a cache, each translation entry corresponding to one of a plurality of page table entries and defining a translation between a first address and a second address, and encoding control information indicative of an attribute of each page table entry; returning, in response to a lookup querying a first lookup address, a corresponding second address when the first lookup address corresponds to one of the plurality of translation entries stored in the cache; modifying at least some of the control information in response to notification of a modification of the attribute in a page table entry; and retaining in the cache at least one translation entry corresponding to the page table entry for use in a subsequent address lookup querying a corresponding first lookup address in response to the notification of the modification of the attribute in the page table entry.

Data processing apparatus and method for address translation

Instruction decoder to decode processing instructions; one or more first registers; first processing circuitry to execute the decoded processing instructions in a first processing mode and configured to execute the decoded processing instructions using the one or more first registers; and control circuitry to execute the decoded processing instructions in a second processing mode using one or more second registers; the instruction decoder being configured to decode processing instructions selected from a first instruction set and a second instruction set in the second processing mode, in which one or both of the first and second instruction sets comprises at least one unique instruction set; the instruction decoder configured to decode one or more mode change instructions to change between the first and second processing mode; and the first processing circuitry configured to change the current processing mode between the first and second processing mode responding to executing mode change instruction.

Processing instructions selected from a first instruction set in a first processing mode and instructions selected from a second different instruction set in a second processing mode

A memory management unit comprises an interface for receiving an address translation request from a device, the address translation request specifying a virtual request to be translated. Translation circuitry translates the virtual address into an intermediate address different from a physical address directly specifying a memory location. The interface provides an address translation response specifying the intermediate address to the device in response to the address translation request. This improves security by avoiding exposure of physical addresses to the device.

Handling address translation requests

Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry. A realm management unit (RMU) is provided to perform realm management operations for managing the realms. The memory access circuitry controls access to a given memory region in dependence on at least one status attribute specifying whether the given memory region is an RMU-private memory region reserved for exclusive access by the RMU.

Realm management unit-private memory regions

An apparatus for processing data comprises memory access circuitry to enforce ownership rights of a plurality of memory regions within a first memory. The memory access circuitry is responsive to a first export command received from a first export command source to perform a first export operation to encrypt the given owned data to form given encrypted data and to store the given encrypted data in a second memory. The memory access circuitry is responsive to a second export command for the given memory region received from a second export command source while the first export operation is being performed to determine whether said second export command source has higher priority than the first export command source and, when the second export command source has a higher priority, to interrupt the first export operation and to perform a second export operation specified by the second export command.

Interrupting export of memory regions

Apparatuses and methods are disclosed for performing data processing operations in main processing circuitry and delegating certain tasks to auxiliary processing circuitry. User-specified instructions executed by the main processing circuitry comprise a task dispatch specification specifying an indication of the auxiliary processing circuitry and multiple data words defining a delegated task comprising at least one virtual address indicator. In response to the task dispatch specification the main processing circuitry performs virtual-to-physical address translation with respect to the at least one virtual address indicator to derive at least one physical address indicator, and issues a task dispatch memory write transaction to the auxiliary processing circuitry comprises the indication of the auxiliary processing circuitry and the multiple data words, wherein the at least one virtual address indicator in the multiple data words is substituted by the at least one physical address indicator.

Task dispatch

There is provided an apparatus for receiving a request from a master to access an input address. Coarse grain access circuitry stores and provides a reference to an area of an output address space in dependence on the input address. One or more fine grain access circuits, each store and provide a reference to a sub-area in the area of the output address space in dependence on the input address. The apparatus forwards the request from the coarse grain access circuitry to one of the one fine grain access circuits in dependence on the input address.

Address space access control

An access frequency caching hardware structure has entries each storing an access frequency counter indicative of a frequency of accesses to a corresponding page of a memory address space. Access frequency tracking circuitry is responsive to a given memory access request requesting access to a target page, to determine whether the access frequency caching hardware structure already includes a corresponding entry which is valid and corresponds to the target page. When the structure includes the corresponding entry, a corresponding access frequency counter specified by the corresponding entry is incremented. In response to a counter writeback event associated with a selected access frequency counter corresponding to a selected page, an update is made to a global access frequency counter corresponding to the selected page within a global access frequency tracking data structure stored in the memory system.

Access frequency caching hardware structure

A realm management unit (RMU) manages ownership of memory regions by realms, each realm corresponding to at least a portion of a software process executed by processing circuitry. Memory access circuitry enforces ownership rights for the regions, with the owner realm having a right to exclude other realms from accessing data stored within its owned region. The memory access circuitry permits execution, from within a current realm, of program code stored in a target memory region having an owner realm other than the current realm, when the target memory region is owned by a code realm and a code realm authorisation tablestored in at least one memory region owned by the current realm indicates that execution of program code from the target memory region is permitted by the current realm.

Code realms

An apparatus has processing circuitry for performing data processing in response to software processes and memory access circuitry for enforcing ownership rights for memory regions. A given memory region is associated with an owner realm specified from a multiple realms with each realm corresponding to a portion of at least one software process. The owner realm has a right to exclude other realms from accessing data stored in the given memory region (including realms executed at a higher privilege level). The realms are managed according to a realm hierarchy in which each realm other than a root realm is a child realm initialised in response to a command triggered by its parent realm. In response to an invalidation command, a realm management unit makes the target realm and any descendant realm of the target realm inaccessible to the processing circuitry.

Invalidation of a target realm in a realm hierarchy

Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry. A realm management unit initialises the realms. The realm management unit is configured to initialise realms including a full realm which corresponds to a given software process and a sub-realm corresponding to a given address range within the given software process.

Sub-realms

A method for locating metadata associated with a first address. The method comprises: accessing a page table structure, a page table entry of said page table structure providing address translation data for use in an address translation process for translating said first address into a second address; extracting () portions of at least two page table entries in the page table structure, determining () a pointer to a metadata table from said portions, and using () the pointer to locate from the metadata table target metadata associated with the first address.

Method for locating metadata

Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry. In response to a first variant of an exception return instruction the processing circuitry returns from processing of an exception while staying within the same realm. In response to a second variant of the exception return instruction the processing circuitry switches processing from a current realm to a destination realm.

Exception return instruction variants for realm-based switching

A data processing apparatus is provided comprising: a plurality of storage circuits to store data. Execution circuitry performs one or more operations using the storage circuits in response to instructions. The instructions include a relinquish instruction. The execution circuitry responds to the relinquish instruction by indicating that at least one of the plurality of storage circuits is an unused storage circuit and the execution circuitry affects execution of future instructions based on the unused storage circuit after executing the relinquish instruction.

Data structure relinquishing

A realm management unit (RMU)manages ownership of memory regions by realms, each realm corresponding to at least a portion of a software process executed by processing circuitry. Memory access circuitryenforces ownership rights for the regions, with the owner realm having a right to exclude other realms from accessing data stored within its owned region. The RMUcontrols transitions of memory regions between region states, including an invalid state, a valid state, and a scrub-commit statein which the memory region is allocated to an owner realm, inaccessible to that owner realm until a scrubbing process has been performed for the memory region to set each storage location of the region to a value uncorrelated with a previous value stored in the storage location, and prevented from being reallocated to a different owner realm.

Growing community of inventors

Cambridge, United Kingdom

Matthew Lucien Evans