National Semiconductor Corporation

Analog Devices,inc.

Texas Instruments Corporation

Analog Devices International Unlimited Company

Matthew Louis Courcy

Gabriele Manganaro

Gil Engel

Carroll Clifton Speir

Reuben Pascal Nelson

Jianguo Yao

John Kevin Behel

Jipeng Li

Matthew D McShea

Kenny Gentile

Martin Clara

Lawrence A Singer

Wenhua William Yang

Jialin Zhao

Robert J LeBoeuf, Ii

David Brian Barkin

Steven C Rose

Gerard E Taylor

James Brinkhurst

Michael J Guidry, Jr

Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.

Bi-directional interface for device feedback

A DAC has a plurality DAC cells, and timing mismatch among the DAC cells can introduce errors in an output of a DAC. An efficient technique can be implemented to extract the timing error of a DAC cell. The technique involves a mixer to mix the timing error to DC (DC stands for direct current, where signal frequency is zero) and a VCO ADC to observe the output of the DAC cell to measure and extract the timing error. A first measurement is made using a first quadrature phase signal and a second measurement is made using a second quadrature phase signal. A difference between the first measurement and the second measurement yields the timing error of the DAC cell. Advantageously, the mixer can be integrated within a voltage-to-current converter of the VCO ADC. The timing error can be corrected in the digital domain or analog domain.

DAC calibration using VCO ADC

Phase control of clock signal based on feedback

Embodiments of the present invention may provide non-invasive techniques for adjusting timing in multistage circuit systems. A multistage circuit system according to embodiments of the present invention may include a plurality of circuit stages coupled to signal lines that carry signals. The system may also include a plurality of load circuits, one provided in for each circuit stage. The load circuits may have inputs coupled to the signal lines that carry the input signals. Each load circuit may include a current source programmable independently of the other load circuits that propagates current through an input transistor in the respective load circuit that receives the signal. The current propagating through the input transistor may provide a load on the corresponding signal line, allowing fine timing adjustment for each circuit stage.

Fine timing adjustment method

Disclosed systems include a clock-multiplying phase locked loop (PLL) generating a clock signal for a DAC comprising a plurality of DAC cells, the systems configured to control that a phase of the DAC output has a predefined relation to a phase of a PLL input reference clock. An exemplary system incorporates an auxiliary DAC cell implemented as a replica of one of the DAC cells of the DAC and operation of the DAC and the auxiliary DAC cell is timed with the same clock signal generated by the PLL, so that outputs of the auxiliary cell and the DAC are phase synchronized by design. The system is configured to ensure that a phase of the auxiliary DAC cell output is related to the phase of the PLL reference clock, which results in a phase of the DAC output also being related to the phase of the PLL reference clock.

Synchronization of outputs from multiple digital-to-analog converters

The present disclosure provides embodiments of an improved current steering switching element for use in a digital to analog (DAC) converter. Typically, each current steering switching element in the DAC converter provides a varying set of currents for converting a digital input signal. Generally, the switches and drivers in the current steering switching elements are scaled down proportionally to the current being provided by the current steering switching element according to a ratio as less and less current is being driven by the switching element in order to overcome timing errors. However, device sizes are limited by the production process. When a switch is not scaled proportionally to the current, settling timing errors are present and affects the performance of the DAC. The improved current steering switching element alleviates this issue of timing errors by replacing the single switch with two complementary current steering switches.

Complementary switches in current switching digital to analog converters

A method of generating a spread spectrum clock signal for a line imaging device including receiving a line length value of the line imaging device, receiving a first clock signal indicative of a system timing signal in the line imaging device, generating a spreading waveform having a frequency as a function of the line length value and having a total number of clock cycles matching the line length value, and modulating the first clock signal using said spreading waveform to generate the spread spectrum clock signal where the spread spectrum clock signal is used for driving the imaging, data sampling and digitizing, and data transfer operation of the line imaging device. The spread spectrum clock has the same clock frequency variation for each scan line of the line imaging device.

Line rate spread spectrum clock generator for use in line imaging systems

A method of operating a line imaging device including receiving a first clock signal indicative of a system timing signal in the line imaging device, generating a second clock signal based on the first clock signal and being unmodulated where the second clock signal being used for driving the imager timing, data sampling and digitizing operations of the line imaging device, and generating a third clock signal based on the first clock signal and being modulated using a spreading waveform where the third clock signal being a spread spectrum clock signal and being used to drive the data transfer operation of the line imaging device.

Mixed domain spread spectrum clocking for use in imaging systems for maximum imaging quality and optimized EMI performance

A common mode controller circuit () for maintaining a common mode voltage (Vcm) at a first node () and a second node () in a sample-and-hold circuit receiving a pair of AC coupled differential input signals (Vinp, Vinn) includes first and second resistors (R/R) and third and fourth resistors (R/R), each set of resistors connected in series between the first and second nodes, and a differential amplifier (A) having an inverting input terminal coupled to a third node () between the first and second resistors, a non-inverting input terminal coupled to a reference voltage (Vref) and an output terminal coupled to a fourth node () between the third and fourth resistors. The common mode voltage is sampled at the third node and the differential amplifier provides a sourcing output current indicative of the difference between the sampled common mode voltage and the reference voltage to drive the fourth node.

Common mode controller for a sample-and-hold circuit

An analog front end for a multi-channel signal processor is provided. The analog front end includes a first stage that is operable to receive a plurality of channel inputs. The first stage includes a ping/pong capacitor array corresponding to each of the channel inputs and an operational amplifier that may be coupled successively to each of the ping/pong capacitor arrays.

System and method for reducing power consumption in a multi-channel signal processor

A data conversion stage circuit () for an opamp-shared pipeline analog-to-digital converter (ADC) () includes an over-range detection and recovery circuit including first and second switches (S, S) connected between respective input terminals () and output terminals () of the opamp () and both controlled by a first control signal, and a logic circuit () coupled to receive the first residue value and compare the first residue value to a pair of high and low comparison voltage levels. The logic circuit asserts the first control signal during a first clock phase when the first residue value is either greater than the high comparison voltage level or less than the low comparison voltage level. The high and low comparison voltage levels define a voltage region outside of a reference voltage range of the data conversion stage circuit where the reference voltage range defines in-range voltage values for the data conversion stage circuit.

Pipeline ADC with memory effects achieving one cycle absolute over-range recovery

A switched-capacitor amplifier circuit including first and second pairs of sampling capacitors for sampling a pair of input signals includes a voltage regulator coupled to receive a first reference voltage and generate a first regulated output voltage related to the first reference voltage and independent of a first power supply voltage; a clock signal generator generating first and second clock signals referenced to the first power supply voltage and third and fourth clock signals referenced to the first regulated output voltage; and a first set of switches coupling the bottom plates of the sampling capacitors to the amplifier, the first set of switches being controlled by the third and fourth clock signals. The circuit may further include a second set of switches coupling the top plates of the sampling capacitors to the input signals, the second set of switches being controlled by the first and second clock signals.

Regulated switch driving scheme in switched-capacitor amplifiers with opamp-sharing

A clock signal duty cycle stabilization system. The system includes a clock signal duty cycle stabilization circuit having an edge detection circuit and a latch circuit. The edge detection circuit is configured to receive an external clock signal and generate an output therefrom. The latch circuit is coupled to receive the output from the edge detection circuit. The latch circuit is configured to produce a rising edge of an internal clock signal and a falling edge of the internal clock signal in accordance with the output of the edge detection circuit.

System for clock duty cycle stabilization

A system and method of generating a clock. A first clock is accessed. A delayed version of the first clock is created. A second clock signal is generated. A first edge of the second clock signal corresponds to a transition of the first clock signal, and a second edge of the second clock signal corresponds to a transition of the delayed version of the first clock signal.

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Fremont, NH, United States of America

Matthew Louis Courcy