Intel Corporation

National Semiconductor Corporation

Matthew James Webb

Daniel Christian Biederman

Ilango S Ganga

Robert G Southworth

Alain Gravel

Jonathan A Dama

John E Gavlik

Aniket A Aphale

Ted Chang

Robert G Hathaway

James B Wieser

Ramsin Michael Ziazadeh

Jose Niell

Vijaya G Ceekala

Chih-Jen Chang

Wing Cheung

Dan Biederman

Sharvil Desai

Multi-port Media Control Channel (MAC) with flexible data-path width. A multi-port receive (RX) MAC block includes multiple RX ports and a plurality of RX circuit blocks comprising an RX MAC pipeline for performing MAC Layer operations on RX data received at the RX ports. The RX circuit blocks are connected with variable-width datapath segments, and the RX MAC block is configured to implement a multi-port arbitration scheme such as a TDM (Time-Division Multiplexed) scheme under which RX data received at a given RX port are forwarded over the variable-width datapath segments using datapath widths associated with that RX port. A multi-port transmit (TX) MAC block implementing a TX MAC pipeline comprising TX circuit blocks connected with variable-width datapath segments is also provided. The RX and TX MAC blocks include CRC modules configured to calculate CRC values on input data received over datapaths having different widths.

Multi-port media access channel (MAC) with flexible data-path width

A compute device can access local or remote accelerator devices for use in processing a received packet. The received packet can be processed by any combination of local accelerator devices and remote accelerator devices. In some cases, the received packet can be encapsulated in an encapsulating packet and sent to a remote accelerator device for processing. The encapsulating packet can indicate a priority level for processing the received packet and its associated processing task. The priority level can override a priority level that would otherwise be assigned to the received packet and its associated processing task. The remote accelerator device can specify a fullness of an input queue to the compute device. Other information can be conveyed by packets transmitted between and among compute devices and remote accelerator devices to assist in determining an accelerator to use or other uses.

Processor related communications

Techniques to operate a time division multiplexing (TDM) media access control (MAC) module include examples of facilitating use of shared resources allocated to ports of a network interface based on a time slot mechanism. The shared resources allocated to process packet data received or sent through the ports of the network interface.

Techniques to operate a time division multiplexing(TDM) media access control (MAC)

Particular embodiments described herein provide for an electronic device that includes at least one processor operating at eight hundred (800) megahertz and can be configured to receive a data stream, parse packets in the data stream, and process at least two (2) full packets from the data stream in a single clock cycle. In an example, the data stream is at least a two hundred (200) gigabit Ethernet data stream and a bus width is at least thirty-two (32) bytes.

Scalable packet processing

Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.

Single-lane, twenty-five gigabit ethernet

A circuit and method are provided for performing built-in test of output signal magnitudes of integrated differential signal generator circuitry. In accordance with one embodiment, first upper and lower reference voltages and second upper and lower reference voltages are received via a plurality of reference electrodes, wherein: a difference between the first and upper and lower reference voltages comprises a first difference magnitude; a difference between the second upper and lower reference voltages comprises a second difference magnitude; and the first difference magnitude is greater than the second difference magnitude. Test signal generator circuitry provides a plurality of binary signals with respective successions of opposing signal states. Differential signal generator circuitry, coupled to the test signal generator circuitry and responsive to the plurality of binary signals, provides a plurality of differential signals having respective magnitudes related to the respective successions of opposing binary signal states. Signal comparison circuitry, coupled to the plurality of reference electrodes and the differential signal generator circuitry, and responsive to the first and second upper and lower reference signals and the plurality of differential signals, provides a plurality of test signals with respective test signal states indicative of whether respective ones of the differential signal magnitudes are within a range defined as being less than the first difference magnitude and greater than the second difference magnitude.

Differential signal generator with built-in test circuitry

There is disclosed an apparatus for controlling a physical layer interface of a network interface card. The apparatus comprises: 1) a read only memory (ROM) for storing an embedded control program; 2) a random access memory for storing a downloadable software control program; and 3) a microcontroller for controlling the physical layer interface, wherein the microcontroller in a first operating mode executes the embedded control program to thereby control the physical layer interface, and wherein the microcontroller in a second operating mode downloads the downloadable software control program from an external processing system and executes the software control program in place of the embedded control program to thereby control the physical layer interface.

Network interface card using physical layer microcontroller and method of operation

There is disclosed an apparatus for controlling a physical layer interface of a network interface card in real time. The apparatus comprises: 1) a first memory for storing a multitasking control program, the multitasking control program comprising a main routine and a plurality of subroutines callable by the main routine; 2) a second memory for storing a plurality of multitasking vectors associated with the multitasking control program; and 3) a microcontroller for executing the multitasking control program, wherein program execution control is transferred from the main routine to a first one of the plurality of subroutines when the first subroutine is called by the main routine and wherein the first subroutine, upon encountering a decision point in the first subroutine that is not yet capable of being decided, updates a first one of the plurality of multitasking vectors associated with the first subroutine with an address of the decision point and transfers program execution control back to the main routine.

Growing community of inventors

Woodland Hills, CA, United States of America

Matthew James Webb