International Business Machines Corporation

Jds Uniphase Corporation

Matthew James Paschal

Ronald Leroy Billau

Vincenzo V Di Luoffo

Brandon William Schulz

Dan Peter Dumarot

James Edward Woodbury

Kevin Paul Demsky

Raymond Alan Richetta

Timothy Joseph Schmerbeck

Patrick Lee Rosno

Dereje G Yilma

Steven John Baumgartner

Eric John Lukes

Nghia Van Phan

Ladd William Freitag

Brent Ray Den Hartog

Daniel Scott Hedin

Daniel Mark Dreps

James David Strom

David W Siljenberg

John Farley Ewen

Bruce George Rudolph

John Edward Sheets, Ii

Todd Alan Christensen

John Francis Bulzacchelli

Glen Arthur Wiedemeier

Mounir Meghelli

Matthew B Baecher

Gautam Gangasani

Trushil N Shah

London Terry Brown

A deskew circuit receives a data signal and a clock signal of differing frequencies and indeterminate phase relationship. The deskew circuit selectively applies a delay to a data signal to obtain a delayed data signal. First and second latches of the deskew circuit latch the delayed data signal based on a rising edge and a falling edge of the clock signal, respectively. The deskew circuit detects a phase difference between output signals of the first and second latches. The deskew circuit adjusts the delay applied to the data signal based on the detected phase difference.

Phase alignment of signals of different frequencies

A first oscillator signal and a second oscillator signal are transmitted to a processing unit. The first oscillator signal has a finite frequency or phase offset relative to the second oscillator signal. A first clock signal that is derived from the first oscillator signal is selected as a primary clock to clock the processing unit. A second clock signal derived from the second oscillator signal is aligned to the first clock signal. If a fault is detected on the first clock signal, the second clock signal is selected as the primary clock to clock the processing unit. Upon being selected as the primary clock, the phase of the second is stretched by one fixed phase for one clock cycle.

Redundant clock switch

A steady-state voltage on an oscillator output can be detected, independent of control signals received from other circuitry, by an oscillator failure detection circuit (OFDC) fabricated within an integrated circuit (IC). The OFDC can, in response to detecting the steady-state voltage, output an oscillator failure signal on a reference fail output. The OFDC can receive, with a first and a second buffer, an oscillator output signal from an oscillator output. Through the use of an electrically interconnected, pull-down device, pull-up network, pull-up device, pull-down network, Schmitt trigger, inverting Schmitt trigger and OR-gate, the OFDC can drive the oscillator failure signal onto an output of the OR-gate electrically connected to a reference fail output (RFO).

Oscillator failure detection circuit

A circuit component comprises a row of transistors. The row may contain a first active FET with a source region and a drain region. The row may also contain a first active dummy FET that shares the source region and that also has a diffusion region. The row may also contain a second active FET and a second active dummy FET, positioned such that the active dummy FETs are located between the active FETs on the row. The row may also have an end positioned such that the first active dummy FET is between the end and the first active FET. A supply of current may be electrically connected to the source diffusion regions. A load region may be electrically connected to the drain region. The first active FET and the first active dummy FET may have gates that share a voltage source or that have their own voltage source.

Field effect transistor structure for reducing contact resistance

Certain aspects of the present disclosure are directed to a circuit for driving a signal at an output node. The circuit generally includes a voltage divider network having a first terminal coupled to the output node. The circuit also includes a first transistor having a gate coupled to a second terminal of the voltage divider network and a plurality of transistors. A gate of each of the plurality of transistors may be coupled to a respective tap node of the voltage divider network, and the plurality of transistors may include a third transistor having a source coupled to a drain of the first transistor. The circuit may also include a second transistor coupled to the first transistor and having a gate coupled to an input node of the circuit.

Bidirectional interface using thin oxide devices

A surveillance video broker arbitrates access by multiple clients to multiple surveillance video sources. Both clients and sources register with the broker. Each source independently specifies respective clients permitted real-time access to its video and conditions of access, if any. Preferably, the video source is a local surveillance domain having one or more cameras, one or more sensors, and a local controller, the source specifying clients or client groups permitted access, and independently specifying conditions of access for each client or client group, where conditions may include scheduled events, non-scheduled events, such as alarms or emergencies, and/or physical proximity. The broker automatically authorizes real-time access according to pre-specified conditions. Preferably, the broker can also arbitrate alert notifications to the clients based on pre-specified notification criteria.

Distributed control of a heterogeneous video surveillance network

Method and apparatus to calibrate sampling phases of a multi-phase sampling system. The method includes on-chip generating a pristine phase reference pattern signal for use in generating at least one reference output signal from a data path; sampling, responsive to a clock signal, the at least one reference output signal to obtain samples; and modifying a phase of the clock signal to align the obtained samples to pattern edges of at least one reference output signal. Both symmetric and asymmetric duty cycle distortion are removed from the pristine phase reference pattern signal input to the data path. The effects of asymmetric distortion in the data path output signal upon the phase calibration are cancelled by periodically inverting the at least one reference output signal. The method adjusts a first phase sampling clock signal output of an electronic phase rotator device to provide an initial alignment setting against a first edge of the reference output signal; and then implements phase calibration logic to align a second phase sampling clock signal against a second edge.

Calibration of sampling phase and aperature errors in multi-phase sampling systems

A gated differential logic circuit can include a header device having a first terminal coupled to a supply voltage, and a second terminal; a second header device having a third terminal coupled to the supply voltage, and a fourth terminal; a footer device having a fifth terminal coupled to ground, and a sixth terminal; and a second footer device having a seventh terminal coupled to ground, and an eighth terminal. The circuit further includes a driver circuit having a first supply terminal coupled to the second terminal and a first ground terminal coupled to the sixth terminal, and a second driver circuit having a second supply terminal coupled to the fourth terminal and a second ground terminal coupled to the eighth terminal. A capacitor can couple the first supply terminal to the second ground terminal, while a second capacitor may couple the second supply terminal to the first ground terminal.

Gated differential logic circuit

Real-time access by a requestor to surveillance video is conditionally pre-authorized dependent on the existence of at least one pre-specified automatically detectable condition, and recorded in a data processing system. A requestor subsequently requests real-time access to the surveillance video (e.g., as a result of an alarm), and if the pre-specified automatically detectable condition is met, access is automatically granted, i.e., without the need for manual intervention. An automatically detectable condition could, e.g., be an alarm condition detected by a sensor at the site of the video surveillance. Alternatively, it could be a locational proximity of the requestor to the site of the video surveillance. Alternatively, it could be a previously defined time interval.

Automated authorization to access surveillance video based on pre-specified events

Real-time access by a public authority emergency responder to surveillance video of a privately-controlled source is conditionally pre-authorized dependent on the existence of at least one pre-specified emergency condition, and recorded in a data processing system. A public authority emergency responder subsequently requests real-time access to the surveillance video (e.g., during an emergency), and if the pre-specified emergency condition is met, access is automatically granted, i.e., without the need for manual intervention. A pre-specified emergency condition could, e.g., be an alarm condition detected by a sensor at the site of the video surveillance, or a declared state of emergency, properly declared by an appropriate public official.

Providing emergency access to surveillance video

The present invention provides a method and apparatus for measuring alignment, rotation and bias of mask layers in semiconductor manufacturing by examining threshold voltage variation.

Mask alignment, rotation and bias monitor utilizing threshold voltage dependence

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Rochester, MN, United States of America

Matthew James Paschal