Micron Technology Incorporated

Lodestar Licensing Group LLC

Matthew J King

Darwin A Clampitt

Indra V Chary

Anilkumar Chandolu

Brett D Lowe

John David Hopkins

Lifang Xu

David A Daycock

Kunal Shrotri

Chandra S Tiwari

Albert Fayrushin

Yi Hu

Matthew Park

Wei Yeeng Ng

Andrew Li

Yongjun Jeff Hu

Jivaan Kishore Jhothiraman

Yiping Wang

Rutuparna Narulkar

Gordon A Haller

Richard J Hill

Roger W Lindsay

Jun Fujiki

Daniel Billingsley

Harsh Narendrakumar Jain

Xiaosong Zhang

Ramey M Abdelrahaman

David Daycock

Jun Fang

Thomas George

Justin B Dorhout

Suresh Ramarajan

Shawn D Lyonsmith

Sidhartha Gupta

M Jared Barclay

Haoyu Li

Gowrisankar Damarla

Sri Sai Sivakumar Vegunta

Kyle A Ritter

Rithu K Bhonsle

John B Matovu

David S Meyaard

Kevin Y Titus

Kevin R Gast

Shashank Saraf

Lisa M Clampitt

Yoshiaki Fukuzumi

Haitao Liu

Jordan D Greenlee

Chris M Carlson

John Mark Meldrim

Everett Allen McTeer

Jian Li

Chet E Carter

David A Kewley

Fei Wang

Yushi Hu

Alex J Schrinsky

Eric Blomiley

Silvia Borsari

Jin Lu

Prakash Rau Mokhna Rau

Merri Lyn Carlson

Justin D Shepherdson

Chris Larsen

Jason Reece

Lance Williamson

Cole Smith

Narula Bilik

Tom George

Michael J Gossman

Bo Zhao

Martin Jared Barclay

Saniya Rathod

Amritesh Rai

Pavithra Natarajan

Zhenyu Bo

Joan M Kash

David Neumeyer

Paolo Tessariol

Adam William Saxler

Anish A Khandekar

Adam L Olson

Shuji Tanaka

Erik R Byers

Umberto Maria Meotto

Diem Thy N Tran

Nicholas R Tapias

Matthew Holland

Shruthi Kumara Vadivel

Michael E Koltonski

Biow Hiem Ong

Joel D Peterson

Christopher R Ritchie

Kye Hyun Baek

Md Zakir Ullah

Tien Minh Quan Tran

Kaiming Luo

Madison D Drake

Kok Siak Tang

A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures. Memory cells vertically extend through the stack structure, and comprise a channel material vertically extending through the stack structure. An additional stack structure vertically overlies the stack structure and comprises additional conductive structures and additional insulative structures. First pillar structures extend through the additional stack structure and vertically overlie a portion of the memory cells. Second pillar structures are adjacent to the first pillar structures and extend through the additional stack structure and vertically overlie another portion of the memory cells. Slot structures are laterally adjacent to the first pillar structures and to the second pillar structures and extend through at least a portion of the additional stack structure. A distance between the first pillar structures and the slot structures is substantially equal to a distance between the second pillar structures and the slot structures.

Microelectronic devices including slot structures, and related electronic systems and methods of forming the microelectronic devices

A microelectronic device includes a stack structure including a vertically alternating sequence of conductive structures and insulating structures arranged in tiers, a dielectric-filled opening vertically extending into the stack structure and defined between two internal sidewalls of the stack structure, a stadium structure within the stack structure and comprising steps defined by horizontal ends of at least some of the tiers, a first ledge extending upward from a first uppermost step of the steps of the stadium structure and interfacing with a first internal sidewall of the two internal sidewalls of the stack structure, and a second ledge extending upward from a second, opposite uppermost step of the steps of the stadium structure and interfacing with a second, opposite internal sidewall of the two internal sidewalls.

Microelectronic devices including stadium structures

Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.

Microelectronic devices including pillars with partially-circular upper portions and circular lower portions, and related methods

A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

Semiconductor devices comprising carbon-doped silicon nitride and related methods

Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 10atoms/cmto about 10atoms/cm. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

Microelectronic devices including conductive structures

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

Memory device including multiple decks of memory cells and pillars extending through the decks

A microelectronic device comprises a stack structure comprising a stack structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, staircase structures within the stack structure and having steps comprising edges of the tiers, and a doped dielectric material adjacent the steps of the staircase structures and comprising silicon dioxide doped with one or more of boron, phosphorus, carbon, and fluorine, the doped dielectric material having a greater ratio of Si—O—Si bonds to water than borophosphosilicate glass. Related methods of forming a microelectronic device and related electronic systems are also disclosed.

Microelectronic devices including stair step structures, and related electronic devices and methods

Some embodiments include an integrated assembly having a base (e.g., a monocrystalline silicon wafer), and having memory cells over the base and along channel-material-pillars. A conductive structure is between the memory cells and the base. The channel-material-pillars are coupled with the conductive structure. A foundational structure extends into the base and projects upwardly to a level above the conductive structure. The foundational structure locks the conductive structure to the base to provide foundational support to the conductive structure.

Foundational supports within integrated assemblies

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Intervening material is formed into the stack laterally-between and longitudinally-along immediately-laterally-adjacent memory block regions. The forming of the intervening material comprises forming pillars laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory-block regions. The pillars individually extend through multiple of each of the first tiers and the second tiers. After forming the pillars, an intervening opening is formed individually alongside and between immediately-longitudinally-adjacent of the pillars. Fill material is formed in the intervening openings. Other embodiments, including structure, are disclosed.

Memory arrays and methods used in forming a memory array comprising strings of memory cells

A microelectronic device includes a pair of stack structures. The pair comprises a lower stack structure and an upper stack structure overlying the lower stack structure. The lower stack structure and the upper stack structure each comprise a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A source region is vertically interposed between the lower stack structure and the upper stack structure. A first array of pillars extends through the upper stack structure, from proximate the source region toward a first drain region above the upper stack structure. A second array of pillars extend through the lower stack structure, from proximate the source region toward a second drain region below the lower stack structure. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.

Microelectronic devices with source region vertically between tiered decks, and related methods and systems

A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically overlying the strings of memory cells, and additional slot structures comprising a dielectric material extending through at least a portion of the additional stack structure and sub-dividing each of the block structures into sub-block structures, the additional slot structures horizontally neighboring the first pillars. Related microelectronic devices, electronic systems, and methods are also described.

Microelectronic devices including tiered stacks including conductive structures isolated by slot structures, and related electronic systems and methods

A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells. The channel structures can be implemented as a segmented portion for drains and a portion opposite a gate. The segmented portion includes one or more fins and one or more non-conductive regions with both fins and non-conductive regions extending vertically from the portion opposite the gate. Variations of a border region for the portion opposite the gate with the segmented portion can include fanged regions extending from the fins into the portion opposite the gate or rounded border regions below the non-conductive regions. Such select gate transistors can be formed using a single photo mask process. Additional devices, systems, and methods are discussed.

Select gate transistor with segmented channel fin

Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rwhich is the mean peak-to-valley distance along the undulating topography. The Ris at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies having rugged material fill, and methods of forming integrated assemblies

Growing community of inventors

Boise, ID, United States of America

Matthew J King