USA As Represented by Secretary of the Navy

Matthew J Kay

Adam Duncan

Matthew Gadlage

James David Ingalls

Austin H Roach

Andrew Mark Howard

Brett J Hamilton

Matthew John Gadladge

Brett Werner

Glenn Berger

Various embodiments include providing a MTJ-based LUT and adding a system that short circuits or causes dielectric layer breakdown of selected MTJ junctions to permanently finalize a desired logic state configuration of selected MTJs that is read out by the LUT. Additional embodiments disable dielectric layer breakdown or short circuit control circuits to prevent further alterations to MTJ that have not had their dielectric layers broken down or shorted out. A control system then alters reading out the MTJ-based LUT to sense original higher and lower resistance values of un-shorted/altered MTJs as a higher resistance state and a shorted or dielectric layer that has been broken down as a lower resistance state. This combines the flexibility of a multiple-time programmable LUT-based FPGA with the security and reliability of a one-time programmable LUT-based FPGA which has characteristics of a fixed logic non-programmable integrated circuit or application specific integrated circuit (ASIC).

Non-volatile multiple time programmable integrated circuit system with selective conversion to one time programmable or permanent configuration bit programming capabilities and related methods

Apparatuses and methods using current-starved ring oscillator biased by floating gate transistors with a variety of applications including as a power-free radiation detector or silicon age determination or odometer system.

Apparatuses and methods using current-starved ring oscillator biased by floating gate transistors with a variety of applications including as a power-free radiation detector or silicon age determination or odometer system

Exemplary systems and methods for inhibiting backend access to an integrated circuit are provided including latch-up circuits triggered by photons, electrons, and ions to create catastrophic failures in integrated circuits. Exemplary systems include latch-up circuits with floating gate bit cells which, when triggered, close the latch-up circuits so that the latch-up circuits can amplify current in a positive feedback loop to create a short circuit to inhibit unauthorized individuals from probing or modifying an integrated circuit.

Systems and methods for inhibiting backend access to integrated circuits by integrating photon and electron sensing latch-up circuits

A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.

Method and system for improving the radiation tolerance of floating gate memories

An irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus is provided. A non-volatile floating gate charge storage device can include a block of floating gate transistors that can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitrite-oxide region, and a control gate region. A structure altering stress effect is applied to the block of transistors to create a passage region in a random number of floating gate regions of floating gate transistors which changes charge storage or electrical characteristics of random elements of the block of transistors. The passage region alters charges on a floating gate region to escape in a different manner than pre-alteration form causing the floating gate region to lose its charge. An apparatus for recording and detecting such differences in pre and post alteration can also be provided.

Irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus

Apparatuses and methods are provided using a plurality of interrupted IC operations to detect various conditions or changes of interest to integrated circuit (IC) elements (e.g., memory cells of NAND Flash memories or floating gate transistor) such as program/erase stress, total ionizing dose, and heavy ion exposure which modify normal IC element bit state changes. An exemplary method can include controlling a plurality of selected IC elements to execute a series of PROGRAM or ERASE operations on all of the plurality of selected elements that are each interrupted or halted before a normal or first time period required for the PROGRAM or ERASE operation has elapsed. An exemplary system records a number of interrupted operations required to cause a state change in each of the plurality of selected IC elements. Embodiments of the invention enable detection of stresses far below at least some thresholds for IC element or bit cell failure.

Methods and apparatuses including one or more interrupted integrated circuit operations for characterizing radiation effects in integrated circuits

An irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus are provided. A non-volatile floating gate charge storage device can include a block of floating gate transistors that can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitrite-oxide region, and a control gate region. A structure altering stress effect is applied to the block of transistors to create a passage region in a random number of floating gate regions of floating gate transistors which changes charge storage or electrical characteristics of random elements of the block of transistors. The passage region alters charges on a floating gate region to escape in a different manner than pre-alteration form causing the floating gate region to lose its charge. An apparatus for recording and detecting such differences in pre and post alteration can also be provided.

Methods and apparatuses for implementing a Physically Unclonable Function (PUF) and random number generator capabilities comprising providing a device under test comprising a plurality of bits comprising integrated circuits each including a capacitor; placing the bits in a first state with charge on selected bit capacitors; stopping bit refresh for a first predetermined time; re-enabling refresh for a second predetermined time to read and refresh charge on all bits; reading all bits and recording addresses of bits that have experienced bit flip from a first state to a second state comprising from '1' to '0' state; performing selecting a plurality of said recorded addresses to generate a PUF or cryptographic key; and performing an operation comprising a test or verification operation with said generated information PUF or key. Various hardware elements are also provided as well as machine readable instructions for implementing and controlling aspects of the invention.

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Jasper, IN, United States of America

Matthew J Kay