Intel Corporation

Matthew J Andrus

Oleg Golonzka

Timothy E Glassman

Hiten Kothari

Nathan Strutt

Dragos Seghete

Namrata S Asuri

Christopher J Wiegand

Daniel Ouellette

Patrick J Hentges

Trinh T Van

Ameya S Chaudhari

An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the interconnect, where an upper portion of the electrode structure has a first width. The RRAM device further includes a switching layer on the electrode structure, where the switching layer has the first width and an oxygen exchange layer, having a second width less than the first width, on a portion of the switching layer. The RRAM device further includes a top electrode above the oxygen exchange layer, where the top electrode has the second width and an encapsulation layer on a portion of the switching layer, where the switching layer extends along a sidewall of the oxygen exchange layer.

Resistive random access memory device and methods of fabrication

A memory device includes a bottom electrode above a substrate, a first switching layer on the bottom electrode, a second switching layer including aluminum on the first switching layer, an oxygen exchange layer on the second switching layer and a top electrode on the oxygen exchange layer. The presence of the second switching layer including aluminum on the first switching layer enables a reduction in electro-forming voltage of the memory device.

Resistive random access memory device with switching multi-layer stack and methods of fabrication

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Hillsboro, OR, United States of America

Matthew J Andrus