International Business Machines Corporation

Sun Microsystems, Inc.

Globalfoundries Inc.

Matthew J Amatangelo

Peter Juergen Klim

Christopher McCall Durham

Robert E Mains

Jeannette Sutherland

Daniel William Bailey

Stephen Larry Runyon

Taqi Nasser Buti

Craig D Eaton

Bill K C Kwan

Shervin Hojat

A processor () includes a clock source (), a central processing unit (CPU) (), and a clock generator (). The clock source () includes an output for providing a periodic clock signal. The CPU () includes an input for receiving a CPU clock signal. The clock generator () includes a first input coupled to the output of the clock source (), a second input for receiving a mode signal that indicates an output frequency, and an output coupled to the input of the CPU (). The clock generator () provides the CPU clock signal using periodic pulse skipping such that the CPU clock signal has a number of transitions over a unit of time corresponding to the output frequency.

Techniques for integrated circuit clock management using pulse skipping

Broadly speaking, a method is provided for evaluating nets in a crosstalk noise analysis. More specifically, a method is provided for evaluating timing window overlap between a pair of nets. The method includes selecting one timing window from each net of the pair of nets for analysis. The method further includes analyzing characteristics of the timing windows selected from the pair of nets to identify a timing window overlap presence, wherein the timing window overlap presence can exist between any two timing windows associated with each net of the pair of nets, respectively.

Method for evaluating nets in crosstalk noise analysis

Given two synchronous clocks which transact data from a transmitter element to a receiver element which are analyzed by static timing, the interval between the transmitting data launch clock edge and the receiving capture clock edge is adjusted from the clock waveforms provided in order to represent the worst case slack situation between these two clocks over time. The amount of this adjustment is determined without unrolling (enumerating) all possible launch/capture pairs for these clocks. The greatest common divisor (GCD) of a transmit clock frequency and a receive clock frequency is determined. An effective phase shift is determined by performing a MOD operation between the GCD and an offset of the transmitter and receiver clocks. An algorithm uses the GCD and effective phase shift to determine a launch/capture interval that corresponds to a critical slack condition.

Determining cycle adjustments for static timing analysis of multifrequency circuits

According to one form of the invention, an apparatus includes first timing circuitry, at least one stage of logic circuitry and second timing circuitry. The first timing circuitry has a first data input and a latch with a latch data input coupled to the first data input and a latch data output coupled to an input of the least one stage of logic circuitry. The second timing circuitry has a latch and an edge detector with respective latch and edge detector data inputs coupled to a data output of the at least one stage of logic circuitry. The edge detector has an output coupled to a control input of the second timing circuitry latch for triggering capture of an output data signal on the data output of the at least one stage of logic circuitry responsive to detecting a signal transition.

Multistage, single-rail logic circuitry and method therefore

A method and apparatus is provided for enabling a static timing tool to analyze and test register files in integrated circuits to find correct paths and ignore detected contention. This is achieved by utilizing pattern matching in the static timing tool and having the tool perform certain operations on the transistors of the pattern matched. The methodology includes considering the write word lines as clock nodes, disabling signal propagation through the memory element components, forcing predetermined internal nodes to be of inverse polarity, establishing signal direction through the circuit elements, and indicating that one or more of the predetermined nodes are not to be reported.

Register file timing using static timing tools

A system, method, and computer program product are disclosed for automatically performing timing checks on a memory cell. A static timing tool is provided that includes multiple, different standard timing elements. Each standard timing element is associated with one or more standard timing checks. The memory cell is represented using one or more of the standard timing elements. Standard timing checks associated with the timing elements used to represent the memory cell are used to verify timing in the memory cell.

Data processing system, method, and product for automatically performing timing checks on a memory cell using a static timing tool

A wafer design layout and method of producing multiple integrated chip types using a single set of masks for a wafer and then at the time the type of chip desired is known, using a few customizing steps to produce the final integrated chip is provided. In one embodiment, the wafer layout includes a plurality of groupings of components and a plurality of dicing channels separating each of the components from others of the components. After the particular type of integrated circuit chip desired is selected, the wafer may then have the final few layers processed and the chips removed using the appropriate dicing channels for the integrated circuit chip desired.

Physical design technique providing single and multiple core microprocessor chips in a single design cycle and manufacturing lot using shared mask sets

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Austin, TX, United States of America

Matthew J Amatangelo