Sicortex, Inc.

Hewlett-packard Development Company, L.p.

Compaq Information Technologies Group, L.p.

Matthew H Reilly

Judson S Leonard

Nitin Dhiroobhai Godiwala

Joel S Emer

Tryggve Fossum

Bruce Edwards

James E Hicks, Jr

Lawrence Colm Stewart

Craig B Zilles

Christopher F Joerg

Rebecca L Stamm

Washington Taylor

Shane Bell

Matthew C Mattina

Chuan-Hua Chang

Systems and methods for arbitrating for virtual channels to prevent livelock in richly-connected multiprocessor computer system. Livelock is prevented in a multiprocessor computer system, in which each of a large plurality processing node has input links and egress links. A virtual channel is assigned to convey the communication. Communication data from the plurality of input links is buffered in cross point buffers. A subset of the cross point buffers bids for, and arbitrates, use of the same one egress link. The virtual channel of the selected communication is identified. It is determined whether any of the other communications bidding for use of the egress link are associated with the identified virtual channel and if so whether any communication has been waiting longer than the selected communication. If so, allowing that communication to use the egress link before the selected communication does.

System and method for arbitration for virtual channels to prevent livelock in a richly-connected multi-processor computer system

Systems and methods for communicating on a richly-connected multiprocessor computer system using a pool of buffers for dynamic association with a virtual channel. Packets are communicated in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology, in which a communication from a source processing node to a target processing node may pass through one or more intermediate nodes en route to the target processing node. A set of virtual channels is associated for each link in the interconnection topology. A first subset of buffers is dedicated for fixed correspondence to virtual channel identifiers, and a second subset of buffers is dedicated for dynamic allocation and assignment to virtual channels.

System and method for communicating on a richly connected multi-processor computer system using a pool of buffers for dynamic association with a virtual channel

Systems and methods for preventing deadlock in richly-connected multiprocessor computer system using dynamic assignment of virtual channels. Deadlock is prevented in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology. Each link in the interconnection topology is associated with a set of virtual channels. Each virtual channel has corresponding communication buffers to store communication data and each virtual channel has an associated virtual channel identifier. Each communication between a source processing node and a target processing node is assigned an initial virtual channel to convey the communication from the source processing node. At an intermediate processing node, a different virtual channel is assigned to convey the communication toward the target processing node, in accordance with pre-defined rules to avoid a cycle of dependency of communication buffer resources.

System and method for preventing deadlock in richly-connected multi-processor computer system using dynamic assignment of virtual channels

Computer system and method using a Kautz-like digraph to interconnect computer nodes and having control back channel between nodes. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)k; The data interconnections from a node x to a node y in the topology satisfy the relationship y=(&#x2212;x*k&#x2212;j) mod O, where 1&#x2266;j&#x2266;k; and each x,y pair includes a unidirectional control link from node y to node x to convey flow control and error information from a receiving node y to a transmitting node x.

Computer system and method using a kautz-like digraph to interconnect computer nodes and having control back channel between nodes

Computer systems and methods using efficient module and backplane tiling to interconnect computer nodes via a Kautz-like digraph. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)k. The interconnections from a node x to a node y in the topology satisfy the relationship y=(&#x2212;x*k&#x2212;j) mod O, where 1&#x2266;j&#x2266;k, and the computing nodes are arranged onto a plurality of modules. Each module has an equal plurality of computing nodes on it. A majority of the inter-node connections are contained on the plurality of modules and a minority of the inter-node connections are inter-module connections. Inter-module connections are routed among modules in parallel on an inter-module connection plane.

Computer system and method using efficient module and backplane tiling to interconnect computer nodes via a Kautz-like digraph

An exception handler for a processor is split into two functional units to permit exceptions to be classified into two categories. The first category of exceptions includes performance critical excepted instructions, while the second category includes non-performance critical excepted instructions. The performance critical exceptions are routed to a speculative exception handler, which resolves the exceptions speculatively, even though the excepted instruction may lie in a speculative path of the program flow. The non-performance critical exceptions are routed to a non-speculative exception handler that only resolves exceptions when the excepted instruction is certain to execute in an actual path of the program flow.

Method and system with multiple exception handlers in a processor

Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.

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Stow, MA, United States of America

Matthew H Reilly