Xilinx, Inc.

Matthew H Klein

David Taylor

Sridhar Subramanian

Jian Tan

Tim Tuan

James M Simkins

Raghunandan Chaware

Sridhar Narayanan

Ronald L Cline

Bart Reynolds

Chen Wei Tseng

Subodh Kumar

Xiaojian Yang

Alan M Frost

Andy DeBaets

Vincent Vendramini

Stephen M Trimberger

Steven P Young

Trevor J Bauer

Brian C Gaide

Atul V Ghia

Patrick J Crotty

Xiao-yu Li

Robert W Wells

Weiguang Lu

Dinesh D Gaitonde

Brendan Farley

John E McGrath

Jason R Bergendahl

James E Ogden

Richard William Swanson

Daniel Y Chung

Goran Hk Bilski

Brian Philofsky

Anthony J Collins

Qi Zhang

Jongheon Jeong

Xiao-Yu Li

Andy H Gan

Glenn O'Rourke

Ketan Sodha

Edward S McGettigan

Uma E Durairajan

Thomas H Strader

Ismed D Hartanto

Karthy Rajasekharan

Chirag Ravishankar

Subodh Gupta

Madan Mohan Patra

Restu I Ismail

Wei Yee Jocelyn Teo

Craig E Taylor

Thao H T Vo

Gregory Meredith

Maithilee Rajendra Kulkarni

Juan Jose Noguera Serra

Joshua Tan

Himanshu Verma

Thao HT Vo

Kumar Subodh

David Y Chung

Andrew J Debaets

Embodiments herein describe assigning integrated circuits with defects as variants of the integrated circuit design. Each variant can deactivate different circuitry in the integrated circuit design. A location of the defect can be matched to a variant that has a deactivated region that covers the defect. The integrated circuit can then be assigned to that variant.

Software defined device variants

Some examples described herein provide for a multi-chip structure including one or more memory dies stacked on a die having a programmable integrated circuit (IC). In an example, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable IC, and the programmable IC includes a memory controller. The first die is on and attached to the package substrate. The second die includes memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.

Multi-chip structure including a memory die stacked on die having programmable integrated circuit

Some examples described herein relate to programmable devices that include a data processing engine (DPE) array that permits shifting of where an application is loaded onto DPEs of the DPE array. In an example, a programmable device includes a DPE array. The DPE array includes DPEs and address index offset logic. Each of the DPEs includes a processor core and a memory mapped switch. The processor core is programmable via one or more memory mapped packets routed through the respective memory mapped switch. The memory mapped switches in the DPE array are coupled together to form a memory mapped interconnect network. The address index offset logic is configurable to selectively modify which DPE in the DPE array is targeted by a respective memory mapped packet routed in the memory mapped interconnect network.

Programmable device having a data processing engine (DPE) array

Embodiments described herein include techniques for providing information regarding a hardware part using a scannable code so that a customer can make an informed decision when placing the hardware part in a larger computing system. A customer may purchase hardware parts that are categorized into a certain bin which has guaranteed range of power consumption or performance. The customer may over design the computing system to accommodate the worst parameter in the range (e.g., the minimum performance or the maximum power consumption) to ensure the timing or power specifications are not violated. Instead, the embodiments herein provide a scannable code on the hardware part which the customer can use to access a database which stores more granular information about the part. The customer can use the performance parameters to make better informed decisions to determine where to place the part in the computing system.

Database lookup using a scannable code for part selection

Methods and apparatus are described for providing and using programmable ICs suitable for meeting the unique desires of large hardware emulation systems. One example method of classifying a programmable IC having impaired circuitry generally includes determining a partitioning of programmable logic resources into two or more groups for classifying the programmable IC, testing the programmable IC to determine at least one location of the impaired circuitry in the programmable logic resources of the programmable IC, and classifying the programmable IC based on the at least one location of the impaired circuitry in relation to the partitioning of the programmable logic resources.

Programmable integrated circuits for emulation

Examples herein describe techniques for forming 3D stacked devices which include a redundant logical layer. The 3D stacked devices include a plurality of semiconductor chips stacked in a vertical direction such that each chip is bonded to a chip above, below, or both in the stack. In one embodiment, each chip is the same&#x2014;e.g., has the same circuitry arranged in the same configuration in the chip. The 3D stacked device provides a redundant logic layer by dividing the chips into a plurality of slivers which are interconnected by inter-chip bridges. For example, the 3D stacked device may include three stacked chips that are divided into three different slivers where each sliver includes a portion from each of the chips. So long as only one of portions in a sliver is nonfunctional, the inter-chip bridges permit the other portions in the sliver to receive and route data.

Redundancy scheme for a 3D stacked device

A programmable logic device includes an integrated circuit die having a programmable fabric region including N identical programmable logic partitions. In some embodiments, N&#x2212;1 of the identical programmable logic partitions are user-programmable. In addition, and in some cases, one of the identical programmable logic partitions is a spare logic partition. In some embodiments, the integrated circuit die further includes a network-on-a-chip (NOC) including a vertical NOC (VNOC) and a horizontal NOC (HNOC). By way of example, the N identical programmable logic partitions are configured to communicate exclusively through the NOC. In some embodiments, a defective one of the N&#x2212;1 identical programmable logic partitions is configured for swapping with the spare logic partition.

Systems and methods for providing defect recovery in an integrated circuit

Embodiments herein describe binning and placement techniques for assembling a multi-die device to improve yield when a customer requests a high performance feature from the device. For example, the multi-die device may include multiple dies that are interconnected to form a single device or package. In one embodiment, the multiple dies are the same semiconductor die (e.g., have the same circuit layout) which are disposed on a common interposer or stacked on each other. The multi-die device can then be attached to a printed circuit board (PCB). Although the dies in the multi-die device may each include the same feature (e.g., a PCIe interface, SerDes interface, transmitter, memory interface, etc.), the multi-die device is assembled so that not all of the dies have a feature that satisfies the high performance requested by the customer. That is, at least one of the die includes a lower performance feature.

Selective per die performance binning

Disclosed approaches for limiting use or a programmable IC involve a provider of programmable ICs generating, using one or more private keys of the provider, one or more signed configuration bitstreams from one or more circuit designs received from a customer. The provider changes the general purpose programmable IC into an application programmable IC that can only be programmed by the one or more signed configuration bitstreams. The application programmable IC and the one or more signed configuration bitstreams are provided from the provider to the customer.

Restricting programmable integrated circuits to specific applications

A method for fabricating integrated circuit (IC) dies and wafers having such dies, are disclosed herein that leverage temporary connection traces during wafer level testing of the functionality of the IC die. In one example, a wafer includes a plurality of IC dies. At least a first IC die of the plurality of IC dies includes a plurality of micro-bumps and a first temporary connection trace formed on an exterior surface of the die body. The plurality of micro-bumps includes at least a first micro-bump and a second micro-bump. The first temporary connection trace electrically couples the first micro-bump and the second micro-bump.

Temporary connection traces for wafer sort testing

Methods and apparatus are described for creating a multi-die package from a wafer without dicing the wafer into individual dies and reassembling the dies on an interposer. One example method generally includes testing a plurality of IC dies disposed on a wafer; disposing one or more connectivity layers above the plurality of IC dies, the one or more connectivity layers comprising one or more electrical conductors configured to connect together two or more of the plurality of dies in each of one or more groups of the IC dies; dicing the wafer having the one or more connectivity layers disposed above the plurality of dies into sets, each set comprising one or more of the plurality of dies, wherein the dicing is based on the one or more groups having IC dies that passed the testing; and packaging at least a portion of the sets of dies.

Multi-die wafer-level test and assembly without comprehensive individual die singulation

An example pulse generation circuit includes a parallel-to-serial circuit configured to convert parallel data to serial data according to parallel clock signal and a serial clock signal, the serial data comprises a sequence of pulses; a clock generator configured to generate a clock signal; and a phase controller configured to generate the serial clock signal from the clock signal based on a phase control signal.

Precision pulse generation using a serial transceiver

In a method for buffering, a buffer buffers data responsive to read and write clock signals. A flag signal from the buffer is for a fill level thereof. The flag signal is toggled responsive to the data buffered being either above or below a set point for the fill level. A phase of the write clock signal is adjusted to a phase of the read clock signal responsive to the toggling of the flag signal. The write clock signal is used to control latency of the buffer. The adjusting of the phase of the write clock signal includes: generating an override signal responsive to the toggling of the flag signal; and inputting the read clock signal and the override signal to a phase adjuster to controllably adjust the phase of the write clock signal to the phase of the read clock signal during operation.

Latency control in a transmitter/receiver buffer

Growing community of inventors

Redwood City, CA, United States of America

Matthew H Klein