Dell Products Inc.

Emc IP Holding Company LLC

Emc Corporation

Matthew H Fredette

Steven T McClure

Uresh K Vahalia

Steve Chalmer

Sorin Faibish

Jean-Pierre Bono

Adnan Sahin

Jonathan I Krasner

Steven R Chalmer

Patrick Brian Riordan

John Forecast

James Marriot Guyer

Jeremy O'Hare

David Reese

Hongliang Tang

Chakib Ouarraoui

Serge Joseph Pirotte

Alexandre Lemay

Lixin Pang

Processes include inertia bias values associated with migration paths and boundaries. When a process scheduler determines that a process is eligible for migration by comparing a process-related variable with a reference value, a new run domain is selected for the process and the inertia bias value specified by the process for the migration path is applied to the process-related variable to obtain a biased process-related variable. The process scheduler only migrates the process to the new run domain responsive to a determination that the process is still eligible for migration by comparing the biased process-related variable with the reference value. Thus, the process creator can specify process-specific tolerances for migration across NUMA boundaries via various paths.

Operating system process scheduler with location inertia

One or more aspects of the present disclosure relate to controlling lock access operations. In embodiments, an instruction corresponding to a program by a processor of a plurality of processors in a computing device is received. In addition, a lock corresponding to a target resource of the instruction is obtained based on a contended or uncontended state of the lock. Further, the instruction is executed contemporaneously with obtaining the lock.

Controlling lock access operations

A hypervisor is configured to bridge I/O operations between the NVMeoPCIe version of the NVMe I/O protocol and the NVMeoF version of the NVMe I/O protocol. By providing a bridging hypervisor, guests can use the NVMePCIe version of the NVMe I/O protocol for storage access operations, while the hypervisor can use the NVMeoF version of the NVMe I/O protocol to implement the storage access operations on attached storage resources of the storage system. The hypervisor handles administrative actions associated with creating, managing, and destroying submission queues and completion queues. Once the desired queue configuration has been created, NVMeoPCIe I/O operations are able to be transparently bridged by the hypervisor, which greatly reduces the amount of processing that would be required if the hypervisor were required to terminate each NVMeoPCIe I/O operation, generate corresponding NVMeoF I/O operations, and keep track of each such pair of I/O operations.

Hypervisor bridging of different versions of an IO protocol

A data storage system with multi-core processors dynamically enables and disables processor cores in order to manage power consumption while maintaining performance. One or more active processor cores are disabled responsive to determining that the current workload can be serviced with fewer active processor cores than are currently enabled while maintaining performance. One or more inactive processor cores are enabled responsive to determining that the current workload cannot be serviced with the currently active processor cores while maintaining performance. Separate utilization thresholds may be implemented for enabling inactive processor cores and disabling active processor cores to promote stability.

Achieving power savings and low latency for storage

A method for managing data includes obtaining, by a hypervisor on a host computing device, a write request for storing first data, and in response to the write request: identifying a first set of memory segments associated with the first data using a memory mapper, wherein the first set of memory segments is associated with a memory device, making a first determination that the memory device is local to the host computing device, and in response to the first determination: storing the first data in the first set of memory segments.

Method and system for providing processor-addressable persistent memory to guest operating systems in a storage system

A method and system for sharing data reduction metadata with storage systems. Specifically, the disclosed method and system entail communicating, to a storage system, information known to host devices from which data (submitted to-be-written to the storage system) may originate. This a priori reduction-pertinent information, which may include the potential to improve storage system efficiency and/or performance at least with respect to data reduction processing of the data submitted to-be-written, had previously been considered incommunicable to the storage system. The disclosed method and system, however, lift this previous limitation and enable communication of any storage system performance-improving information, applicable to the data submitted to-be-written, to the storage system.

Method and system for sharing data reduction metadata with storage systems

Operating a hypervisor includes running a hypervisor as a thread of an underlying operating system and loading a guest operating system using the hypervisor based on the thread of the underlying operating system, where the hypervisor runs independently of the guest operating system and independently of other hypervisors running as other threads of the underlying operating system. The hypervisor may be a first hypervisor and operating a hypervisor may further include running a second hypervisor nested with the first hypervisor, where the guest operating system may be loaded using both the first hypervisor and the second hypervisor. The underlying operating system may be an operating system of a storage system.

Nested hypervisors with peripheral component interconnect pass-through

Operating at least one hypervisor includes running a first hypervisor as a first thread of an underlying operating system, running a second hypervisor as a second thread of the underlying operating system, loading a first guest operating system using the first hypervisor based on the first thread of the underlying operating system, loading a second guest operating system using the second hypervisor based on the second thread of the underlying operating system, and scheduling sharing of resources of the underlying system between the first hypervisor and the second hypervisor according to a scheduler of the underlying operating system, where the first hypervisor and the second hypervisor run independently of each other. The scheduler of the underlying operating system may schedule fractional time shares for the first hypervisor and the second hypervisor to access the same resource.

Extended fractional symmetric multi-processing capabilities to guest operating systems

Controlling access to resources using independent and nested hypervisors in a storage system environment

Global memory of a storage system may be used to provide NVRAM capabilities to guest operating systems accessing the storage system. The non-volatility of NVRAM (i.e. that retains its information when power is turned off) provides that an NVRAM device provided by global memory may be used as a journaling device to track storage operations and facilitate recovery and/or failover processing in a storage system without needing to add additional hardware and/or other installed devices. Use of the global memory according to the system described herein to provide an NVRAM device, that may function as a journaling device, provides for the speeding up of transactions, thereby improving metadata intensive operations performance and reducing recovery time and/or failover time of a storage system without adding additional hardware support.

Growing community of inventors

Belmont, MA, United States of America

Matthew H Fredette