Intel Corporation

Micron Technology Incorporated

Matthew Goldman

Balaji Srinivasan

Mark Alan Helm

Pranav Kalavade

Kerry Dean Tedrow

Hernan Adolfo Castro

Aliasgar S Madraswala

Derchang Kau

Doyle W Rivers

Uday Chandrasekhar

Wayne D Tran

Sungho Park

Krishna Kumar Parat

Jawad Basit Khan

Paul D Ruby

Robert W Faber

Nathan Franklin

Gerald J Barkley

Rezaul Haque

Saad Monasa

Ningde Xie

Alec W Smidt

Jaydip Bharatkumar Patel

Ahsanur Rahman

Dung C Nguyen

Thomas F Ryan

An apparatus comprises a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits.

Method and apparatus for treatment of state confidence data retrieved from a non-volatile memory array

An apparatus may include a processor circuit a processor circuit to retrieve data from a non-volatile memory, and a multistrobe read module operable on the processor circuit to set a read operation to read a memory cell over a multiplicity of sense operations, where each sense operation is performed under a different sense condition. The multistrobe read module may be further operable to schedule a new sense operation to succeed a prior sense operation of the multiplicity of sense operations without recharge of the wordline when a value of one or more read condition is within a preset range. Other embodiments are disclosed and claimed.

Method and system to obtain state confidence data using multistrobe read of a non-volatile memory

The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (V) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on Vand a detected memory cell voltage V.

Reference architecture in a cross-point memory

Various embodiments are generally directed to an apparatus, method and other techniques to retrieve data from a non-volatile memory, and to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. Embodiments also include an apparatus, method and other techniques to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits.

This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.

Memory cell sensing

Devices and methods facilitate memory device operation in all bit line architecture memory devices. In at least one embodiment, memory cells comprising alternating rows are concurrently programmed by row and concurrently sensed by row at a first density whereas memory cells comprising different alternating rows are concurrently programmed by row and concurrently sensed by row at a second density. In at least one additional embodiment, memory cells comprising alternating tiers of memory cells are programmed and sensed by tier at a first density and memory cells comprising different alternating tiers of memory cells are programmed and sensed by tier at a second density.

Memory devices and operating methods for a memory device

Embodiments of the invention describe methods, systems and apparatuses to improve solid state device (SSD) write speed by efficiently utilizing error correction code executed for the device. SSDs may be comprised of several NAND memory devices. It is understood that such devices tend to have a raw bit error rate (RBER) that is related to the program/erase cycle count for the device. Embodiments of the invention efficiently use system ECC by changing the operating conditions of the SSD to better utilize the robustness of the implemented ECC algorithm. For example, embodiments of the invention may alter the programming voltage supplied to an SSD to increase write speed; such an increase may increase the RBER of the device, but will not affect the accuracy of such operations due to the ECC that is provisioned for end of life storage fidelity (i.e., the RBER that will occur at the end of life).

Adjustable programming speed for NAND memory devices

A multi-level cell memory device performs a read by providing a stepped voltage waveform on a wordline, and comparing cell currents to a substantially constant reference current. Prior to the application of the stepped voltage waveform, the wordline may share charge with another circuit node.

Multi-level memory cell sensing

A serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.

Serially sensing the output of multilevel cell arrays

An apparatus and method for pre-charging an intermediate node for high-speed wordlines for accessing memory cells in high-speed memory arrays. The apparatus pre-charges a local capacitance located between a wordline supply voltage and the wordline to a voltage level that is greater than the wordline supply voltage. Once the wordline is selected, the charge stored on the local capacitance may be quickly shared with the capacitance of the wordline. The wordline supply voltage may be applied to the local capacitance to provide small, incremental voltage to move the wordline to its final voltage thereby improving the response time of the system.

Apparatuses and methods for pre-charging intermediate nodes for high-speed wordline

The various embodiments of the present invention provide high precision reference devices, methods, and systems. A high precision reference device may include a plurality of reference cells to receive bias voltages and to provide a cell reference, and an averaging stage coupled to the reference cells to generate an average reference that is the average of the cell references. Other devices, methods, and systems are also claimed and described.

High precision reference devices and methods

In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.

Growing community of inventors

Folsom, CA, United States of America

Matthew Goldman