Sambanova Systems, Inc.

Matthew Feldman

Yaqi Zhang

Raghu Prabhakar

Weiwei Chen

Matthew Vilim

Mark Wagner

A statically reconfigurable dataflow architecture processor (SRDAP) performs an N-dimensional affine transform specified by a matrix on an input image to produce an output image includes L address pattern memory units (PMUs) comprising a memory arranged as a vector of L banks, and L corresponding data PMUs. Each data PMU receives a copy of the input image. In parallel: each address PMU writes an L-vector of addresses of input pixels to the vector of L banks and reads a single address of the written L-vector of addresses from a predetermined bank corresponding to a PMU number of the address PMU among the L address PMUs, and each data PMU receives the single address from the corresponding address PMU and uses it to read a single input pixel from the data PMU memory. A tree of pattern compute units coalesces the L single input pixels into an L-vector of input pixels.

Dataflow architecture processor statically reconfigurable to perform N-dimensional affine transformation in parallel manner by replicating copies of input image across multiple scratchpad memories

A method and system for integrating buffer views into buffer access operations in reconfigurable computing environments. The method includes detecting, in a buffer allocation statement comprising a tensor indexing expression, a buffer view indicator and one or more buffer view parameters. The buffer view parameters are lowered into the tensor indexing expression, according to the buffer view indicator, to produce a modified tensor indexing expression. The buffer view indicator is removed from a buffer allocation statement to produce a modified buffer allocation statement and allocating a buffer according to the modified buffer allocation statement. The system implements the described method and further includes a non-transitory computer readable medium for executing the disclosed method.

Method and system for integrating buffer views into buffer access operations in reconfigurable computing environments

A system comprises an array of reconfigurable units including a plurality of pattern compute units (PCUs) and a plurality of pattern memory units (PMUs), and a compiler configured to receive a tensor including a plurality of memory access patterns of a first type (read) and a second type (write) located in a logical memory of the compiler. Each memory access pattern includes a memory access particular to that type. The compiler is configured to create a plurality of duplicates of the tensor and assign one or more contexts of any type to the duplicate tensors, such that no two contexts of the same type are in the same duplicate tensor. The compiler is configured to trim the duplicate tensors to retain portions including its corresponding assigned contexts remove portions that are inconsequential to the assigned contexts and dispatch the assigned contexts from each duplicate tensor to one or more PMUs.

Duplication of tensors for memory allocation in a reconfigurable data processor

A method for partitioning executable operations for a reconfigurable computing system includes receiving a set of expressions comprising a plurality of operations and dependencies for those operations, partitioning the plurality of operations into selected executable partitions wherein each selected executable partition conforms to resource constraints for a reconfigurable unit of the reconfigurable computing system. Partitioning the plurality of operations into selected executable partitions may include seeding a candidate partition with an operation, recursively generating an additional candidate partition for each operation adjacent to the candidate partition whose dependent operations are already within the candidate partition or a previously selected partition, and selecting a best candidate partition based on resource cost. A corresponding system and computer-readable medium are also disclosed herein. The system includes a partitioning module that that partitions the plurality of operations into selected executable partitions according to the method describe above.

Partitioning dataflow operations for a reconfigurable computing system through recursive candidate generation

A system includes a reconfigurable dataflow processor that comprises an array of compute units and an array of memory units interconnected with a switching fabric. The reconfigurable dataflow processor can be configured to execute a plurality of tensor indexing expressions and access the array of memory units according to a memory unit partitioning solution.

Memory unit partitioning solutions for reconfigurable dataflow computing systems

A method for integrating buffer views into buffer access operations in a reconfigurable computing environment includes detecting, in an instruction stream for a reconfigurable dataflow unit (RDU), a buffer allocation statement comprising a tensor indexing expression, a buffer view indicator and one or more buffer view parameters. The method also includes lowering the buffer view parameters into the indexing expression according to the buffer view indicator to produce a modified tensor indexing expression, removing the buffer view indicator from the buffer allocation statement to produce a modified buffer allocation statement and allocating a buffer according to the modified buffer allocation statement. The modified buffer allocation statement may include the modified tensor indexing expression. A corresponding system and computer readable medium are also disclosed herein.

Integrating buffer views into buffer access operations in a coarse-grained reconfigurable computing environment

A system includes a parser that receives and parses source code for a reconfigurable dataflow processor, a tensor expression extractor configured to extract tensor indexing expressions from the source code, a logical memory constraint generator that converts the tensor indexing expressions to logical memory indexing constraints, a grouping module that groups the logical memory indexing constraints into concurrent access groups and a memory partitioning module that determines a memory unit partitioning solution for each concurrent access group. The system also includes reconfigurable dataflow processor that comprises an array of compute units and an array of memory units interconnected with a switching fabric. The reconfigurable dataflow processor may be configured to execute the plurality of tensor indexing expressions and access the array of memory units according to the memory unit partitioning solution. A corresponding method and computer-readable medium are also disclosed herein.

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Oakland, CA, United States of America

Matthew Feldman