Sun Microsystems, Inc.

Intel Corporation

Matthew E Becker

Todd A Hinck

Eileen H You

Qiang Zhang

Alan Fiedler

Karl W Wyatt

Larry R Tate

Georgios Asmanis

Peter Redmond O'Brien

Marc E Lamere

Zibing Yang

Micah C Knapp

Harry R Fair

Chen Li Lin

Jose Robins

Thomas E Dillinger

Daniel J Flees

Chung Lau Chan

Jonathan A White

In one embodiment, the present invention includes a system having an electromagnetic coupler probe to electromagnetically sample signals from a device under test or a link under test and a receiver, e.g., configured as an integrated circuit that is to receive the sampled electromagnetic signals from the probe and output digital signals corresponding thereto. Other embodiments are described and claimed.

Receiver for recovering and retiming electromagnetically coupled data

According to an embodiment of the invention, a method and apparatus for signal modulation are described. According to an embodiment of the invention, a method comprises producing and transferring a modulated signal. The modulation of the signal is over a plurality of amplitude levels, including at least a first amplitude level, a second amplitude level and a third amplitude level, and over a plurality of time slots, including at least a first time slot, a second time slot, and a third time slot. The modulated signal transitions from the first amplitude level to the second amplitude level in the first phase slot, remains at the second amplitude level in the second time slot, and transitions from the second amplitude level to the third amplitude level in a third time slot.

Signal modulation

In at least one embodiment an apparatus is provided that includes an electromagnetic coupler probe to provide sampled electromagnetic signals and an electronics component to receive the sampled electromagnetic signals from the electromagnetic coupler probe and to provide recovered sampled electromagnetic signals. Other embodiments may be described and claimed.

Apparatus to receive signals from electromagnetic coupler

In accordance with the present invention, a method, system, computer system, and computer program product for considering clock skew in designing digital systems with latch-controlled circuits are provided. The disclosure teaches a method for determining whether logic operations can be performed within the available time and allows detailed modeling of clock skew for different domains of the integrated circuit. Taking clock skew into account for each domain, worst-case timing paths can be determined for circuits controlled by either flip-flops or latches. A design of an integrated circuit can be revised or verified using the method taught. The disclosure envisions that integrated circuits, printed circuit boards, computer systems and other components will be manufactured based upon designs developed with the method taught.

Timing analysis of latch-controlled digital circuits with detailed clock skew analysis

Methods and systems for improving a logic circuit are described. By using a voltage reducer for connecting a power-supply to a virtual ground, the voltage reducer reduces the voltage supplied by the power-supply to the virtual ground during one phase of the clock, thereby increasing the speed and efficiency of the logic circuit.

Virtual ground circuit

A method for integrating population count operations with bit shift operations has been developed. The method can be used for incrementing a pointer by a population count of a sparse vector. The method further provides for balancing the input loads at the inputs of the population count and bit shift circuits so that the execution of operations is more balanced, which, in effect, increases computational speed and efficiency. An apparatus that integrates population count circuitry and bit shift circuitry has also been developed. The apparatus comprises a plurality of dynamic stages followed by static stages. The dynamic stages involve the use of dynamic nodes which represent values dependent upon values of individual bits in the pointer and the sparse vector. The apparatus further allows for an expansion through circuit repetition so that the topology of the apparatus can change according to the size of the pointer and sparse vector.

Dynamic popcount/shift circuit

A method of creating a black box timing model for a digital circuit. The digital circuit is characterized by a block model having at least one input and at least one output. The method determines a delay statement for the output of the block model. The method also determines an input set-up constraint for the input of the block model. The input set-up constraint is based upon the delay statement. The model is then used with a static timing analyzer to accurately model a flow-through circuit.

Black box timing model for latch-based systems

A method and a system for static timing analysis of a latch-based circuit. A netlist data structure represents the latch-based circuit. The method statically analyzes the netlist data structure and produces timing information for signal paths within the latch-based circuit. The signal paths are filtered using path termination information, which specifies where paths end. The path termination information distinguishes a first signal path that terminates at a latch from a second signal path that flows through that same latch.

Path filtering for latch-based systems

An asymmetric arbiter provides a fast signal path and a slow signal path. Signals may travel over the fast signal path in substantially less time than it takes for the signals to travel over the slow signal path. The fast signal path may be configured so as to impart only a minimal amount of delay. Signals that are to be frequently arbitrated by the arbiter may be applied to the fast signal path so as to minimize the delay introduced by the arbiter. The arbiter may include circuitry for detecting metastable conditions.

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Montgomery, AL, United States of America

Matthew E Becker